Verilog: Fix parsing initializers

Import upstream CTags fix for parsing Verilog initalizers
(fixes parsing of test bug2747828.v).

tagmanager/ctags/verilog.c

@@ -229,6 +229,7 @@ static void tagNameList (const verilogKind kind, int c)
 		c = skipWhite (c);
 		if (c == '=')
 		{
+			c = skipWhite (vGetc ());
 			if (c == '{')
 				skipPastMatch ("{}");
 			else

tests/ctags/bug2747828.v.tags

@@ -1,3 +1,2 @@
 # format=tagmanager
-9<EFBFBD>16384<EFBFBD>0
 ramaddr_0Ì16384Ö0