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Verilog: Fix parsing initializers

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Import upstream CTags fix for parsing Verilog initalizers
(fixes parsing of test bug2747828.v).
This commit is contained in:
Colomban Wendling 2013-07-19 17:09:57 +02:00
parent c7e0fba6ca
commit e0ef859c7f
2 changed files with 1 additions and 1 deletions
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1
tagmanager/ctags/verilog.c
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@ -229,6 +229,7 @@ static void tagNameList (const verilogKind kind, int c)
c = skipWhite (c); c = skipWhite (c);
if (c == '=') if (c == '=')
{ {
c = skipWhite (vGetc ());
if (c == '{') if (c == '{')
skipPastMatch ("{}"); skipPastMatch ("{}");
else else

1
tests/ctags/bug2747828.v.tags
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@ -1,3 +1,2 @@
# format=tagmanager # format=tagmanager
9<EFBFBD>16384<EFBFBD>0
ramaddr_0Ì16384Ö0 ramaddr_0Ì16384Ö0