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cycv: support for registers

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aiju 2020-01-13 23:22:35 +00:00
parent 561346d07f
commit 639500b748
4 changed files with 33 additions and 4 deletions
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1
sys/src/9/cycv/dat.h
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@ -203,6 +203,7 @@ struct DevConf
#define mpcore ((ulong*)MPCORE_BASE) #define mpcore ((ulong*)MPCORE_BASE)
#define resetmgr ((ulong*)RESETMGR_BASE) #define resetmgr ((ulong*)RESETMGR_BASE)
#define sysmgr ((ulong*)SYSMGR_BASE) #define sysmgr ((ulong*)SYSMGR_BASE)
#define l3 ((ulong*)L3_BASE)
/*dmacopy*/ /*dmacopy*/
#define SRC_INC (1<<0) #define SRC_INC (1<<0)

33
sys/src/9/cycv/devarch.c
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@ -9,6 +9,8 @@
#define fpga ((ulong*) FPGAMGR_BASE) #define fpga ((ulong*) FPGAMGR_BASE)
enum { REMAP = 0x0 / 4 };
enum { Timeout = 3000 }; enum { Timeout = 3000 };
enum { enum {
@ -56,6 +58,8 @@ static Dirtab archdir[Qmax] = {
}; };
static int narchdir = Qbase; static int narchdir = Qbase;
static Physseg *axi;
static Ref fpgawopen; static Ref fpgawopen;
enum { FPGABUFSIZ = 65536 }; enum { FPGABUFSIZ = 65536 };
static uchar *fpgabuf; static uchar *fpgabuf;
@ -119,7 +123,11 @@ fpgaconf(void)
[10] {1, 4, COMP|AESMAYBE|PORFAST|FPP32}, [10] {1, 4, COMP|AESMAYBE|PORFAST|FPP32},
[14] {1, 4, COMP|AESMAYBE|FPP32} [14] {1, 4, COMP|AESMAYBE|FPP32}
}; };
axi->attr |= SG_FAULT;
procflushpseg(axi);
flushmmu();
if((fpga[FPGAPINS] & FPGA_POWER_ON) == 0) if((fpga[FPGAPINS] & FPGA_POWER_ON) == 0)
error("FPGA powered off"); error("FPGA powered off");
msel = fpga[FPGASTAT] >> 3 & 0x1f; msel = fpga[FPGASTAT] >> 3 & 0x1f;
@ -187,6 +195,10 @@ fpgafinish(void)
return; return;
} }
fpga[FPGACTRL] &= ~HPSCONFIG; fpga[FPGACTRL] &= ~HPSCONFIG;
axi->attr &= ~SG_FAULT;
procflushpseg(axi);
flushmmu();
} }
static long static long
@ -256,13 +268,26 @@ archclose(Chan* c)
} }
} }
static void void
archreset(void) archinit(void)
{ {
Physseg seg;
fpga[FPGAINTEN] = 0; fpga[FPGAINTEN] = 0;
fpga[FPGAEOI] = -1; fpga[FPGAEOI] = -1;
fpga[FPGAINTTYPE] = -1; fpga[FPGAINTTYPE] = -1;
intrenable(FPGAMGRIRQ, fpgairq, nil, LEVEL, "fpgamgr"); intrenable(FPGAMGRIRQ, fpgairq, nil, LEVEL, "fpgamgr");
resetmgr[BRGMODRST] &= ~7;
l3[REMAP] = 0x18;
memset(&seg, 0, sizeof seg);
seg.attr = SG_PHYSICAL | SG_DEVICE | SG_NOEXEC | SG_FAULT;
seg.name = "axi";
seg.pa = 0xFF200000;
seg.size = 0x200000;
axi = addphysseg(&seg);
} }
static Chan* static Chan*
@ -275,7 +300,7 @@ Dev archdevtab = {
'P', 'P',
"arch", "arch",
archreset, devreset,
devinit, devinit,
devshutdown, devshutdown,
archattach, archattach,

2
sys/src/9/cycv/io.h
View File

@ -9,9 +9,11 @@
#define FPGAMGRDATA 0xFFB90000 #define FPGAMGRDATA 0xFFB90000
#define OCRAM 0xFFFF0000 #define OCRAM 0xFFFF0000
#define DMAS_BASE 0xFFE01000 #define DMAS_BASE 0xFFE01000
#define L3_BASE 0xFF800000
/*RESETMGR*/ /*RESETMGR*/
#define PERMODRST (0x14/4) #define PERMODRST (0x14/4)
#define BRGMODRST (0x1C/4)
/*SYSMGR*/ /*SYSMGR*/
#define FPGA_MODULE (0x28/4) #define FPGA_MODULE (0x28/4)

1
sys/src/9/cycv/main.c
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@ -302,6 +302,7 @@ main(void)
bootlinks(); bootlinks();
else else
links(); links();
archinit();
chandevreset(); chandevreset();
pageinit(); pageinit();
userinit(); userinit();