fa8935426b
* Implemented all R-type arithmetic/logical instructions * Implemented all I-type arithmetic/logical instructions * Implemented all load and store instructions * Implemented all of RV64I except FENCE
434 lines
13 KiB
Zig
434 lines
13 KiB
Zig
const std = @import("std");
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const DW = std.dwarf;
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// TODO: this is only tagged to facilitate the monstrosity.
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// Once packed structs work make it packed.
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pub const Instruction = union(enum) {
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R: packed struct {
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opcode: u7,
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rd: u5,
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funct3: u3,
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rs1: u5,
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rs2: u5,
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funct7: u7,
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},
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I: packed struct {
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opcode: u7,
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rd: u5,
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funct3: u3,
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rs1: u5,
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imm0_11: u12,
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},
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S: packed struct {
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opcode: u7,
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imm0_4: u5,
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funct3: u3,
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rs1: u5,
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rs2: u5,
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imm5_11: u7,
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},
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B: packed struct {
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opcode: u7,
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imm11: u1,
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imm1_4: u4,
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funct3: u3,
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rs1: u5,
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rs2: u5,
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imm5_10: u6,
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imm12: u1,
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},
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U: packed struct {
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opcode: u7,
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rd: u5,
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imm12_31: u20,
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},
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J: packed struct {
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opcode: u7,
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rd: u5,
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imm12_19: u8,
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imm11: u1,
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imm1_10: u10,
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imm20: u1,
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},
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// TODO: once packed structs work we can remove this monstrosity.
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.R => |v| @bitCast(u32, v),
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.I => |v| @bitCast(u32, v),
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.S => |v| @bitCast(u32, v),
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.B => |v| @intCast(u32, v.opcode) + (@intCast(u32, v.imm11) << 7) + (@intCast(u32, v.imm1_4) << 8) + (@intCast(u32, v.funct3) << 12) + (@intCast(u32, v.rs1) << 15) + (@intCast(u32, v.rs2) << 20) + (@intCast(u32, v.imm5_10) << 25) + (@intCast(u32, v.imm12) << 31),
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.U => |v| @bitCast(u32, v),
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.J => |v| @bitCast(u32, v),
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};
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}
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fn rType(op: u7, fn3: u3, fn7: u7, rd: Register, r1: Register, r2: Register) Instruction {
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return Instruction{
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.R = .{
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.opcode = op,
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.funct3 = fn3,
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.funct7 = fn7,
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.rd = @enumToInt(rd),
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.rs1 = @enumToInt(r1),
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.rs2 = @enumToInt(r2),
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},
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};
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}
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// RISC-V is all signed all the time -- convert immediates to unsigned for processing
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fn iType(op: u7, fn3: u3, rd: Register, r1: Register, imm: i12) Instruction {
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const umm = @bitCast(u12, imm);
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return Instruction{
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.I = .{
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.opcode = op,
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.funct3 = fn3,
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.rd = @enumToInt(rd),
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.rs1 = @enumToInt(r1),
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.imm0_11 = umm,
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},
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};
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}
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fn sType(op: u7, fn3: u3, r1: Register, r2: Register, imm: i12) Instruction {
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const umm = @bitCast(u12, imm);
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return Instruction{
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.S = .{
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.opcode = op,
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.funct3 = fn3,
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.rs1 = @enumToInt(r1),
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.rs2 = @enumToInt(r2),
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.imm0_4 = @truncate(u5, umm),
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.imm5_11 = @truncate(u7, umm >> 5),
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},
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};
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}
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// Use significance value rather than bit value, same for J-type
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// -- less burden on callsite, bonus semantic checking
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fn bType(op: u7, fn3: u3, r1: Register, r2: Register, imm: i13) Instruction {
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const umm = @bitCast(u13, imm);
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if (umm % 2 != 0) @panic("Internal error: misaligned branch target");
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return Instruction{
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.B = .{
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.opcode = op,
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.funct3 = fn3,
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.rs1 = @enumToInt(r1),
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.rs2 = @enumToInt(r2),
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.imm1_4 = @truncate(u4, umm >> 1),
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.imm5_10 = @truncate(u6, umm >> 5),
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.imm11 = @truncate(u1, umm >> 11),
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.imm12 = @truncate(u1, umm >> 12),
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},
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};
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}
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// We have to extract the 20 bits anyway -- let's not make it more painful
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fn uType(op: u7, rd: Register, imm: i20) Instruction {
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const umm = @bitCast(u20, imm);
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return Instruction{
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.U = .{
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.opcode = op,
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.rd = @enumToInt(rd),
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.imm12_31 = umm,
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},
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};
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}
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fn jType(op: u7, rd: Register, imm: i21) Instruction {
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const umm = @bitcast(u21, imm);
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if (umm % 2 != 0) @panic("Internal error: misaligned jump target");
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return Instruction{
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.J = .{
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.opcode = op,
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.rd = @enumToInt(rd),
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.imm1_10 = @truncate(u10, umm >> 1),
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.imm11 = @truncate(u1, umm >> 1),
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.imm12_19 = @truncate(u8, umm >> 12),
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.imm20 = @truncate(u1, umm >> 20),
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},
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};
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}
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// The meat and potatoes. Arguments are in the order in which they would appear in assembly code.
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// Arithmetic/Logical, Register-Register
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pub fn add(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b000, 0b0000000, rd, r1, r2);
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}
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pub fn sub(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b000, 0b0100000, rd, r1, r2);
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}
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pub fn @"and"(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b111, 0b0000000, rd, r1, r2);
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}
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pub fn @"or"(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b110, 0b0000000, rd, r1, r2);
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}
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pub fn xor(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b100, 0b0000000, rd, r1, r2);
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}
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pub fn sll(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b001, 0b0000000, rd, r1, r2);
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}
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pub fn srl(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b101, 0b0000000, rd, r1, r2);
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}
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pub fn sra(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b101, 0b0100000, rd, r1, r2);
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}
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pub fn slt(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b010, 0b0000000, rd, r1, r2);
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}
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pub fn sltu(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0110011, 0b011, 0b0000000, rd, r1, r2);
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}
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// Arithmetic/Logical, Register-Register (32-bit)
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pub fn addw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b000, rd, r1, r2);
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}
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pub fn subw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b000, 0b0100000, rd, r1, r2);
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}
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pub fn sllw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b001, 0b0000000, rd, r1, r2);
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}
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pub fn srlw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b101, 0b0000000, rd, r1, r2);
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}
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pub fn sraw(rd: Register, r1: Register, r2: Register) Instruction {
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return rType(0b0111011, 0b101, 0b0100000, rd, r1, r2);
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}
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// Arithmetic/Logical, Register-Immediate
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pub fn addi(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b000, rd, r1, imm);
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}
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pub fn andi(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b111, rd, r1, imm);
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}
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pub fn ori(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b110, rd, r1, imm);
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}
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pub fn xori(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b100, rd, r1, imm);
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}
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pub fn slli(rd: Register, r1: Register, shamt: u6) Instruction {
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return iType(0b0010011, 0b001, rd, r1, shamt);
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}
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pub fn srli(rd: Register, r1: Register, shamt: u6) Instruction {
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return iType(0b0010011, 0b101, rd, r1, shamt);
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}
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pub fn srai(rd: Register, r1: Register, shamt: u6) Instruction {
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return iType(0b0010011, 0b101, rd, r1, (1 << 10) + shamt);
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}
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pub fn slti(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0010011, 0b010, rd, r1, imm);
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}
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pub fn sltiu(rd: Register, r1: Register, imm: u12) Instruction {
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return iType(0b0010011, 0b011, rd, r1, @bitCast(i12, imm));
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}
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// Arithmetic/Logical, Register-Immediate (32-bit)
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pub fn addiw(rd: Register, r1: Register, imm: i12) Instruction {
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return iType(0b0011011, 0b000, rd, r1, imm);
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}
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pub fn slliw(rd: Register, r1: Register, shamt: u5) Instruction {
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return iType(0b0011011, 0b001, rd, r1, shamt);
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}
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pub fn srliw(rd: Register, r1: Register, shamt: u5) Instruction {
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return iType(0b0011011, 0b101, rd, r1, shamt);
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}
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pub fn sraiw(rd: Register, r1: Register, shamt: u5) Instruction {
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return iType(0b0011011, 0b101, rd, r1, (1 << 10) + shamt);
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}
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// Upper Immediate
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pub fn lui(rd: Register, imm: i20) Instruction {
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return uType(0b0110111, rd, imm);
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}
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pub fn auipc(rd: Register, imm: i20) Instruction {
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return uType(0b0010111, rd, imm);
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}
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// Load
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pub fn ld(rd: Register, offset: i12, base: Register) Instruction {
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return iType(0b0000011, 0b011, rd, base, offset);
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}
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pub fn lw(rd: Register, offset: i12, base: Register) Instruction {
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return iType(0b0000011, 0b010, rd, base, offset);
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}
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pub fn lwu(rd: Register, offset: i12, base: Register) Instruction {
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return iType(0b0000011, 0b110, rd, base, offset);
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}
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pub fn lh(rd: Register, offset: i12, base: Register) Instruction {
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return iType(0b0000011, 0b001, rd, base, offset);
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}
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pub fn lhu(rd: Register, offset: i12, base: Register) Instruction {
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return iType(0b0000011, 0b101, rd, base, offset);
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}
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pub fn lb(rd: Register, offset: i12, base: Register) Instruction {
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return iType(0b0000011, 0b000, rd, base, offset);
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}
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pub fn lbu(rd: Register, offset: i12, base: Register) Instruction {
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return iType(0b0000011, 0b100, rd, base, offset);
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}
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// Store
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pub fn sd(rs: Register, offset: i12, base: Register) Instruction {
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return sType(0b0100011, 0b011, base, rs, offset);
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}
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pub fn sw(rs: Register, offset: i12, base: Register) Instruction {
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return sType(0b0100011, 0b010, base, rs, offset);
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}
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pub fn sh(rs: Register, offset: i12, base: Register) Instruction {
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return sType(0b0100011, 0b001, base, rs, offset);
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}
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pub fn sb(rs: Register, offset: i12, base: Register) Instruction {
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return sType(0b0100011, 0b000, base, rs, offset);
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}
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// Fence
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// TODO: implement fence
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// Branch
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pub fn beq(r1: Register, r2: Register, offset: u13) Instruction {
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return bType(0b1100011, 0b000, r1, r2, offset);
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}
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pub fn bne(r1: Register, r2: Register, offset: u13) Instruction {
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return bType(0b1100011, 0b001, r1, r2, offset);
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}
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pub fn blt(r1: Register, r2: Register, offset: u13) Instruction {
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return bType(0b1100011, 0b100, r1, r2, offset);
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}
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pub fn bge(r1: Register, r2: Register, offset: u13) Instruction {
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return bType(0b1100011, 0b101, r1, r2, offset);
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}
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pub fn bltu(r1: Register, r2: Register, offset: u13) Instruction {
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return bType(0b1100011, 0b110, r1, r2, offset);
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}
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pub fn bgeu(r1: Register, r2: Register, offset: u13) Instruction {
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return bType(0b1100011, 0b111, r1, r2, offset);
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}
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// Jump
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pub fn jal(link: Register, offset: i21) Instruction {
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return jType(0b1101111, link, offset);
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}
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pub fn jalr(link: Register, offset: i12, base: Register) Instruction {
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return iType(0b1100111, 0b000, link, base, offset);
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}
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// System
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pub const ecall = iType(0b1110011, 0b000, .zero, .zero, 0x000);
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pub const ebreak = iType(0b1110011, 0b000, .zero, .zero, 0x001);
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};
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// zig fmt: off
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pub const RawRegister = enum(u5) {
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x0, x1, x2, x3, x4, x5, x6, x7,
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x8, x9, x10, x11, x12, x13, x14, x15,
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x16, x17, x18, x19, x20, x21, x22, x23,
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x24, x25, x26, x27, x28, x29, x30, x31,
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pub fn dwarfLocOp(reg: RawRegister) u8 {
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return @enumToInt(reg) + DW.OP_reg0;
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}
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};
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pub const Register = enum(u5) {
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// 64 bit registers
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zero, // zero
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ra, // return address. caller saved
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sp, // stack pointer. callee saved.
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gp, // global pointer
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tp, // thread pointer
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t0, t1, t2, // temporaries. caller saved.
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s0, // s0/fp, callee saved.
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s1, // callee saved.
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a0, a1, // fn args/return values. caller saved.
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a2, a3, a4, a5, a6, a7, // fn args. caller saved.
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s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, // saved registers. callee saved.
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t3, t4, t5, t6, // caller saved
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pub fn parseRegName(name: []const u8) ?Register {
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if(std.meta.stringToEnum(Register, name)) |reg| return reg;
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if(std.meta.stringToEnum(RawRegister, name)) |rawreg| return @intToEnum(Register, @enumToInt(rawreg));
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return null;
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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inline for(callee_preserved_regs) |cpreg, i| {
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if(self == cpreg) return i;
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}
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return null;
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}
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pub fn dwarfLocOp(reg: Register) u8 {
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return @as(u8, @enumToInt(reg)) + DW.OP_reg0;
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}
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};
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// zig fmt: on
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pub const callee_preserved_regs = [_]Register{
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.s0, .s1, .s2, .s3, .s4, .s5, .s6, .s7, .s8, .s9, .s10, .s11,
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};
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