6 Commits

Author	SHA1	Message	Date
Eleanor Bartle	fa8935426b	Cleaned up RISC-V instruction creation, added 32-bit immediates (#6077) ... * Implemented all R-type arithmetic/logical instructions * Implemented all I-type arithmetic/logical instructions * Implemented all load and store instructions * Implemented all of RV64I except FENCE	2020-08-18 00:30:00 -04:00
Andrew Kelley	8282f4271c	stage2: basic support for parameters .debug_info ... see #6014	2020-08-11 22:23:32 -07:00
pfg	ea3cc777cc	stage2: riscv test case	2020-08-04 14:38:33 -07:00
pfg	0b53a2d996	stage2: riscv 0 argument non-nested function calls	2020-08-04 14:38:33 -07:00
pfg	1fd99ed324	stage2: riscv hello world	2020-08-04 14:38:33 -07:00
pfg	52ae2b10aa	stage2: starting on a riscv64 backend	2020-08-04 14:38:33 -07:00