95 Commits

Author SHA1 Message Date
Vexu
6ab0ac161e
stage2: slice return type analysis 2020-09-03 15:05:47 +03:00
Vexu
9a59cdcd41
stage2: various small type fixes 2020-09-03 15:05:10 +03:00
Sahnvour
575fbd5e35 hash_map: rename to ArrayHashMap and add new HashMap implementation 2020-09-02 00:17:50 +02:00
Vexu
bcd04089eb stage2: add helpful error message for invalid for operands 2020-08-26 19:50:56 -07:00
Andrew Kelley
e97157f71c stage2: codegen for conditional branching
* Move branch-local register and stack allocation metadata to the
   function-local struct. Conditional branches clone this data in order
   to restore it after generating machine code for a branch.
   Branch-local data is now only the instruction table mapping *ir.Inst
   to MCValue.
 * Implement conditional branching
   - Process operand deaths
   - Handle register and stack allocation metadata
 * Avoid storing unreferenced or void typed instructions into
   the branch-local instruction table.
 * Fix integer types reporting the wrong value for hasCodeGenBits.
 * Remove the codegen optimization for eliding length-0 jumps. I need to
   reexamine how this works because it was causing invalid jumps to be
   emitted.
2020-08-25 22:44:18 -07:00
Vexu
5de9aac749 stage2: error set types 2020-08-24 15:36:42 -07:00
Vexu
16d7db59ed stage2: anyframe and error union types 2020-08-24 15:36:42 -07:00
joachimschmidt557
b2254023e4 stage2: Implement setReg, call, ret, asm for ARM
These changes enable a Hello World example. However, all implemented
codegen is not yet feature-complete.

- asm only supports 'svc #0' at the moment
- call only supports leaf functions at the moment
- setReg uses a naive method at the moment
2020-08-23 22:33:47 +02:00
Vexu
d312d64c9a stage2: slice types 2020-08-20 16:42:48 -07:00
Vexu
9568248450 stage2: complex pointer types 2020-08-20 16:42:48 -07:00
Vexu
ebfe723f3c stage2: implement rest of simple pointer types 2020-08-20 16:42:48 -07:00
Vexu
ab8a9a6605 stage2: fix astgen of decl ref, add test for global consts 2020-08-19 16:12:29 -07:00
Vexu
338a495648 stage2: implement global variables 2020-08-19 16:12:29 -07:00
Vexu
e0b01bd4a9
stage2: enum literals 2020-08-18 14:28:33 +03:00
Vexu
31d8efc6b3
stage2: validate param and variable types 2020-08-18 13:57:09 +03:00
Vexu
7c15c9428e
stage2: array types 2020-08-18 12:36:00 +03:00
Vexu
13b2f1e90b
address review feedback 2020-08-17 19:21:03 +03:00
Vexu
012fac255f
stage2: fix optimization causing wrong optional child types 2020-08-17 14:26:32 +03:00
Vexu
6b2ce9d1e9 stage2: split unwrap_optional to safe and unsafe verions 2020-08-13 08:12:17 -07:00
Vexu
5c1fe58613 stage2: gen optional types 2020-08-13 08:12:17 -07:00
Vexu
75eaf15740 stage2: add optional types 2020-08-13 08:12:17 -07:00
Andrew Kelley
8282f4271c stage2: basic support for parameters .debug_info
see #6014
2020-08-11 22:23:32 -07:00
pfg
e3352db986 stage2: riscv correctly aligned functions 2020-08-04 14:38:33 -07:00
Andrew Kelley
4beff80b2f stage2: codegen handles undefined values
* `optimize_mode` is passed to `link.File` and stored there
 * improve the debugging function `Module.dumpInst`
 * get rid of `Value.the_one_possible_value` in favor of a few more
   specific values for different types. This is less buggy, one less
   footgun.
 * `Type.onePossibleValue` now returns a `?Value` instead of `bool`.
 * codegen handles undefined values. `undef` is a new `MCValue` tag.
   It uses 0xaa values depending on optimization mode. However
   optimization mode does not yet support scope overrides.
 * link.zig: move the `Options` field from `File.Elf` and `File.C` to
   the base struct.
   - fix the Tag enum to adhere to style conventions
 * ZIR now supports emitting undefined values.
 * Fix the logic of comptime math to properly compare against zero using
   the `compareWithZero` function.
2020-07-29 02:29:37 -07:00
Andrew Kelley
99d2d9bf64 stage2: fix format() of mutable pointer types 2020-07-29 02:29:37 -07:00
Andrew Kelley
5ccee4c986 stage2: more progress towards mutable local variables
* implement sema for runtime deref, store pointer, coerce_to_ptr_elem,
   and store
 * identifiers support being lvalues, except for decls is still TODO
 * codegen supports load, store, ref, alloc
 * introduce more MCValue union tags to support pointers
 * add load, ref, store typed IR instructions
 * add Type.isVolatilePtr
2020-07-29 02:29:36 -07:00
Andrew Kelley
d726c2a2d3 self-hosted: beginnings of stack allocation
Comment out non-x86_64 architectures for now in codegen.zig, because
they all have compile errors for their codepaths anyway, and it was
bloating the compilation speed and memory usage when stage1 tried to
build self-hosted. Here's the panic message:

"Backend architectures that don't have good support yet are commented
out, to improve compilation performance. If you are interested in one
of these other backends feel free to uncomment them. Eventually these
will be completed, but stage1 is slow and a memory hog."

This is a workaround to lower the time it takes to build self-hosted
with stage1 as well as use less memory. It should fix the CI.

Additionally:
 * Add `single_mut_pointer` support to `Type`
 * Trivial implementation of stack allocation in codegen.zig. It does
   not deal with freeing yet, and it's missing the stack pointer
   adjustment prologue.
 * Add the `alloc` IR instruction and semantic analysis for `alloc` ZIR
   instruction.
2020-07-28 01:43:04 -07:00
Andrew Kelley
a92990f993 stage2: implement enough for assert() function to codegen 2020-07-14 02:24:12 -07:00
Andrew Kelley
25b1c00c72 stage2: add implicit return void where applicable 2020-07-13 00:08:21 -07:00
Noam Preil
3bad1c16cc
Get basic return test working 2020-07-13 01:49:04 -04:00
Vexu
e85fe13e44
run zig fmt on std lib and self hosted 2020-07-11 20:41:19 +03:00
Andrew Kelley
aa92446365 stage2: implement function parameters
In codegen.zig, the std.Target.Cpu.Arch is now generally available as a
comptime value where needed. This is a tradeoff that causes the compiler
binary to be more bloated, but gives us higher performance, since the
optimizer can optimize per architecture (which is usually how compilers
are designed anyway, with different code per-architecture), and it also
allows us to use per-architecture types, such as a Register enum that is
specific to the comptime-known architecture.

Adds abiSize method to Type.
2020-06-28 19:45:10 -04:00
Andrew Kelley
130c7fd23b self-hosted: working towards conditional branching test case
New features:
 * Functions can have parameters in semantic analysis. Codegen
   is not implemented yet.
 * Support for i8, i16, i32, i64, u8, u16, u32, u64 primitive
   identifiers.
 * New ZIR instructions: arg, block, and breakvoid

Implementation details:

 * Move Module.Body to ir.Body
 * Scope.Block gains a parent field and an optional Label field
 * Fix bug in integer type equality comparison.

Here's the test case I'm working towards:

```
@void = primitive(void)
@i32 = primitive(i32)
@fnty = fntype([@i32, @i32], @void)

@0 = str("entry")
@1 = export(@0, "entry")

@entry = fn(@fnty, {
  %0 = arg(0)
  %1 = arg(1)
  %2 = add(%0, %1)
  %3 = int(7)
  %4 = block("if", {
    %neq = cmp(%2, neq, %3)
    %5 = condbr(%neq, {
      %6 = unreachable()
    }, {
      %7 = breakvoid("if")
    })
  })
  %11 = returnvoid()
})
```

$ ./zig-cache/bin/zig build-obj test.zir
test.zir:9:12: error: TODO implement function parameters for Arch.x86_64

That's where I left off.
2020-06-26 02:30:14 -04:00
Andrew Kelley
5aa3f56773 self-hosted: fix test regressions
I'm allowing incremental compilation of ZIR modules to be broken. This
is not a real use case of ZIR, and the feature requires a lot of code
duplication with incremental compilation of Zig AST (which works great).
2020-06-24 20:28:52 -04:00
Andrew Kelley
7e58c56ca7 self-hosted: implement Decl lookup
* Take advantage of coercing anonymous struct literals to struct types.
 * Reworks Module to favor Zig source as the primary use case.
   Breaks ZIR compilation, which will have to be restored in a future commit.
 * Decl uses src_index rather then src, pointing to an AST Decl node
   index, or ZIR Module Decl index, rather than a byte offset.
 * ZIR instructions have an `analyzed_inst` field instead of Module
   having a hash table.
 * Module.Fn loses the `fn_type` field since it is redundant with
   its `owner_decl` `TypedValue` type.
 * Implement Type and Value copying. A ZIR Const instruction's TypedValue
   is copied to the Decl arena during analysis, which allows freeing the
   ZIR text instructions post-analysis.
 * Don't flush the ELF file if there are compilation errors.
 * Function return types allow arbitrarily complex expressions.
 * AST->ZIR for function calls and return statements.
2020-06-18 17:12:56 -04:00
Andrew Kelley
cf654b52d6 stage2: -femit-zir respects decl names and supports cycles 2020-06-08 15:16:40 -04:00
Andrew Kelley
0bd89979fd stage2: handle deletions and better dependency resolution
* Deleted decls are deleted; unused decls are also detected as deleted.
   Cycles are not yet detected.
 * Re-analysis is smarter and will not cause a re-analysis of dependants
   when only a function body is changed.
2020-05-28 22:42:13 -04:00
Andrew Kelley
81a01bd481 fix codegen of sentinel-terminated arrays and .got alignment
we now have an exit(0) program working
2020-05-14 16:34:04 -04:00
Andrew Kelley
0986dcf1cf self-hosted: fix codegen and resolve some analysis bugs 2020-05-14 13:20:27 -04:00
Andrew Kelley
619159cf48 self-hosted: rework the memory layout of ir.Module and related types
* add TypedValue.Managed which represents a Type, a Value, and some
   kind of memory management strategy.
 * introduce an analysis queue
 * flesh out how incremental compilation works with respect to exports
 * ir.text.Module is only capable of one error message during parsing
 * link.zig no longer has a decl table map and instead has structs that
   exist directly on ir.Module.Decl and ir.Module.Export
 * implement primitive .text block allocation
 * implement linker code for updating Decls and Exports
 * implement null Type

Some supporting std lib changes:
 * add std.ArrayList.appendSliceAssumeCapacity
 * add std.fs.File.copyRange and copyRangeAll
 * fix std.HashMap having modification safety on in ReleaseSmall builds
 * add std.HashMap.putAssumeCapacityNoClobber
2020-05-12 01:02:48 -04:00
Andrew Kelley
a32d3a85d2 rework self-hosted compiler for incremental builds
* introduce std.ArrayListUnmanaged for when you have the allocator
   stored elsewhere
 * move std.heap.ArenaAllocator implementation to its own file. extract
   the main state into std.heap.ArenaAllocator.State, which can be
   stored as an alternative to storing the entire ArenaAllocator, saving
   24 bytes per ArenaAllocator on 64 bit targets.
 * std.LinkedList.Node pointer field now defaults to being null
   initialized.
 * Rework self-hosted compiler Package API
 * Delete almost all the bitrotted self-hosted compiler code. The only bit
   rotted code left is in main.zig and compilation.zig
 * Add call instruction to ZIR
 * self-hosted compiler ir API and link API are reworked to support
   a long-running compiler that incrementally updates declarations
 * Introduce the concept of scopes to ZIR semantic analysis
 * ZIR text format supports referencing named decls that are declared
   later in the file
 * Figure out how memory management works for the long-running compiler
   and incremental compilation. The main roots are top level
   declarations. There is a table of decls. The key is a cryptographic
   hash of the fully qualified decl name. Each decl has an arena
   allocator where all of the memory related to that decl is stored.
   Each code block has its own arena allocator for the lifetime of
   the block. Values that want to survive when going out of scope in
   a block must get copied into the outer block. Finally, values must
   get copied into the Decl arena to be long-lived.
 * Delete the unused MemoryCell struct. Instead, comptime pointers are
   based on references to Decl structs.
 * Figure out how caching works. Each Decl will store a set of other
   Decls which must be recompiled when it changes.

This branch is still work-in-progress; this commit breaks the build.
2020-05-10 02:05:54 -04:00
Andrew Kelley
28729efe29 ZIR: implement return instruction 2020-05-01 06:47:20 -04:00
Andrew Kelley
6b0f7de247 ZIR: add cmp and condbr instructions 2020-05-01 06:47:20 -04:00
Andrew Kelley
d58233b361 ir: improve ZIR emission enough to emit hello world 2020-04-22 03:08:50 -04:00
Andrew Kelley
b1a86040dd ir: emit zir for fntype 2020-04-22 00:26:37 -04:00
Andrew Kelley
2c11acf807 ir: analyze fieldptr instruction 2020-04-21 21:14:56 -04:00
Andrew Kelley
2cdbb5f472 ir: analyze int casting 2020-04-21 19:48:59 -04:00
Andrew Kelley
8671e8d6d4 ir: analyze fntype instruction 2020-04-21 17:06:09 -04:00
Andrew Kelley
fb63ba2577 ir: type coercion skeleton 2020-04-21 13:24:25 -04:00
Andrew Kelley
4c7507cceb ir: semantic analysis skeleton 2020-04-21 00:56:30 -04:00