The ARM backend uses several tricks to support selection of
VFP3_D16/VFP3_D32 when ocamlopt is invoked, which introduces
interferences with non-existing floating-point registers when
the VFP3_D16 fpu option is used. These invalid interferences
must be skipped while coloring the graph.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13229 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
The interference graph no longer contains "ill-typed" interferences
between registers of different class, so we no longer need to test
in the coloring algorithm.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13208 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
The coloring algorithm uses only the "well-typed" interferences (registers
with same class). This is because we don't assign the same stack slot to
registers of different register class.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13207 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
Use rev16/movt to implement direct 16-bit byte-swap operation
(ARMv6T2 and above) and rev to implement the 32-bit byte-swap
operation (ARMv6 and above).
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13203 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
Sets allow for faster insertion than ordered lists, while also supporting
iteration according to the comparison function.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13150 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
Instead of generating a unique quadword constant for each and every
floating point constant use within a function, we now collect the floating
point constants on a per-module basis, and generate only one quadword
per floating point constant.
This affects only the amd64 and i386 ports (both Unix/Linux/OS X and Windows).
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13149 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
There's no need to first split the registers into constrained/unconstrained
sets first and transform these sets into a list using an additional pass;
instead we can directly place the registers on lists, where the constrained
list is sorted by spill cost.
Afterwards all that's left to do is to assign locations to the constrained
and unconstrained registers by traversing the lists.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13145 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
This combines the preallocation of spilled registers and splitting of
the remaining registers into constrained and unconstrained, and thereby
saves one pass on the register set.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13143 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
so that r10 and r11 are no longer used for parameter passing,
and can therefore be destroyed by the dynamic loader without harm.
(Cherry-picked from version/4.00, commit 12907).
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@12908 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
The Thumb-2 TBH instruction supports only forward jumps, which is what is
usually generated for Lswitch. But in some rare cases, the compiler can
generate backward jumps for Lswitch. To properly support these cases, we
emit appropriate trampolines (following the TBH) for these backward jumps
as necessary.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@12548 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
Add hooks in Asmgen to allow external developers to add
new passes on the typedtree, lambda, clambda and cmm trees.
A library 'ocamlopt.cm{a/xa}' is installed, with optmain.cm{x/o},
so that developers can create new ocamlopt executables containing
these new passes.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@12370 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
Benedikt Meurer
Fabrice Le Fessant
Xavier Leroy
Xavier Clerc
Alain Frisch
Damien Doligez