remove all $Id keywords
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@13013 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02master
parent
0a6f6a7857
commit
def31744f9
2
Makefile
2
Makefile
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@ -10,8 +10,6 @@
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# #
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#########################################################################
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# $Id$
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# The main Makefile
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include config/Makefile
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@ -10,8 +10,6 @@
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# #
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#########################################################################
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# $Id$
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# The main Makefile
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include config/Makefile
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4
README
4
README
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@ -129,7 +129,3 @@ To be effective, bug reports should include a complete program
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configuration you are using (machine type, etc).
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You can also contact the implementors directly at caml@inria.fr.
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----
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$Id$
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@ -10,8 +10,6 @@
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Machine-specific command-line options *)
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let pic_code = ref true
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@ -10,8 +10,6 @@
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Emission of x86-64 (AMD 64) assembly code *)
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open Cmm
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Emission of x86-64 (AMD 64) assembly code, MASM syntax *)
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module StringSet =
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@ -10,8 +10,6 @@
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Description of the AMD64 processor *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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open Cmm
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open Arch
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open Reg
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@ -10,8 +10,6 @@
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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let _ = let module M = Schedgen in () (* to create a dependency *)
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(* Scheduling is turned off because the processor schedules dynamically
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@ -10,8 +10,6 @@
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Instruction selection for the AMD64 *)
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open Arch
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@ -11,8 +11,6 @@
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Specific operations for the ARM processor *)
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open Format
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Emission of ARM assembly code *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Description of the ARM processor *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Reloading for the ARM *)
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let fundecl f =
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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open Arch
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open Mach
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Instruction selection for the ARM processor *)
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open Arch
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* From lambda to assembly code *)
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open Format
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* From lambda to assembly code *)
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val compile_implementation :
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Build libraries of .cmx files *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Build libraries of .cmx files *)
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open Format
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Link a set of .cmx/.o files and produce an executable *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Link a set of .cmx/.o files and produce an executable or a plugin *)
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open Format
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* "Package" a set of .cmx/.o files into one .cmx/.o file having the
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original compilation units as sub-modules. *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* "Package" a set of .cmx/.o files into one .cmx/.o file having the
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original compilation units as sub-modules. *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* A variant of the "lambda" code with direct / indirect calls explicit
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and closures explicit too *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* A variant of the "lambda" code with direct / indirect calls explicit
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and closures explicit too *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Introduction of closures, uncurrying, recognition of direct calls *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Introduction of closures, uncurrying, recognition of direct calls *)
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val intro: int -> Lambda.lambda -> Clambda.ulambda
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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type machtype_component =
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Addr
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| Int
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Second intermediate language (machine independent) *)
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type machtype_component =
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Translation from closed lambda to C-- *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Translation from closed lambda to C-- *)
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val compunit: int -> Clambda.ulambda -> Cmm.phrase list
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Format of .cmx, .cmxa and .cmxs files *)
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(* Each .o file has a matching .cmx file that provides the following infos
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* From C-- to assembly code *)
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open Format
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* From C-- to assembly code *)
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val phrase: Cmm.phrase -> unit
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Register allocation by coloring of the interference graph *)
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open Reg
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Register allocation by coloring of the interference graph *)
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val allocate_registers: unit -> unit
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Combine heap allocations occurring in the same basic block *)
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open Mach
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Combine heap allocations occurring in the same basic block *)
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val fundecl: Mach.fundecl -> Mach.fundecl
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Compilation environments for compilation units *)
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open Config
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Compilation environments for compilation units *)
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open Cmx_format
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Generation of assembly code *)
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val fundecl: Linearize.fundecl -> unit
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Common functions for emitting assembly code *)
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open Debuginfo
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Common functions for emitting assembly code *)
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val output_channel: out_channel ref
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Machine-specific command-line options *)
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let fast_math = ref false
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Emission of Intel 386 assembly code *)
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module StringSet = Set.Make(struct type t = string let compare = compare end)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Emission of Intel 386 assembly code, MASM syntax. *)
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module StringSet =
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Description of the Intel 386 processor *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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open Cmm
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open Arch
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open Reg
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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let () = let module M = Schedgen in () (* to create a dependency *)
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(* Scheduling is turned off because our model does not fit the 486
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Instruction selection for the Intel x86 *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Construction of the interference graph.
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Annotate pseudoregs with interference lists and preference lists. *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Construction of the interference graph.
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Annotate pseudoregs with interference lists and preference lists. *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Transformation of Mach code into a list of pseudo-instructions. *)
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open Reg
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Transformation of Mach code into a list of pseudo-instructions. *)
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type label = int
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Liveness analysis.
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Annotate mach code with the set of regs live at each point. *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Liveness analysis.
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Annotate mach code with the set of regs live at each point. *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Representation of machine code by sequences of pseudoinstructions *)
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type integer_comparison =
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Representation of machine code by sequences of pseudoinstructions *)
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type integer_comparison =
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Specific operations for the PowerPC processor *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Emission of PowerPC assembly code *)
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module StringSet = Set.Make(struct type t = string let compare = compare end)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Description of the Power PC *)
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open Misc
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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(* Reloading for the PowerPC *)
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let fundecl f =
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(* *)
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(***********************************************************************)
|
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|
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(* $Id$ *)
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(* Instruction scheduling for the Power PC *)
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open Arch
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(* *)
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(***********************************************************************)
|
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(* $Id$ *)
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(* Instruction selection for the Power PC processor *)
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open Misc
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|
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(* *)
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(***********************************************************************)
|
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(* $Id$ *)
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(* Pretty-printing of C-- code *)
|
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open Format
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|
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@ -10,8 +10,6 @@
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(* *)
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(***********************************************************************)
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||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Pretty-printing of C-- code *)
|
||||
|
||||
open Format
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Pretty-printing of linearized machine code *)
|
||||
|
||||
open Format
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Pretty-printing of linearized machine code *)
|
||||
|
||||
open Format
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Pretty-printing of pseudo machine code *)
|
||||
|
||||
open Format
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Pretty-printing of pseudo machine code *)
|
||||
|
||||
open Format
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Processor descriptions *)
|
||||
|
||||
(* Instruction selection *)
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
open Cmm
|
||||
|
||||
type t =
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Pseudo-registers *)
|
||||
|
||||
type t =
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Insert load/stores for pseudoregs that got assigned to stack locations. *)
|
||||
|
||||
val fundecl: Mach.fundecl -> Mach.fundecl * bool
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Insert load/stores for pseudoregs that got assigned to stack locations. *)
|
||||
|
||||
open Misc
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
class reload_generic : object
|
||||
method reload_operation :
|
||||
Mach.operation -> Reg.t array -> Reg.t array -> Reg.t array * Reg.t array
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Instruction scheduling *)
|
||||
|
||||
open Reg
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Instruction scheduling *)
|
||||
|
||||
type code_dag_node =
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Instruction scheduling *)
|
||||
|
||||
val fundecl: Linearize.fundecl -> Linearize.fundecl
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Selection of pseudo-instructions, assignment of pseudo-registers,
|
||||
sequentialization. *)
|
||||
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Selection of pseudo-instructions, assignment of pseudo-registers,
|
||||
sequentialization. *)
|
||||
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Selection of pseudo-instructions, assignment of pseudo-registers,
|
||||
sequentialization. *)
|
||||
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Specific operations for the Sparc processor *)
|
||||
|
||||
open Format
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Emission of Sparc assembly code *)
|
||||
|
||||
open Misc
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Description of the Sparc processor *)
|
||||
|
||||
open Misc
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Reloading for the Sparc *)
|
||||
|
||||
let fundecl f =
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
open Cmm
|
||||
open Mach
|
||||
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Instruction selection for the Sparc processor *)
|
||||
|
||||
open Cmm
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Insertion of moves to suggest possible spilling / reloading points
|
||||
before register allocation. *)
|
||||
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Insertion of moves to suggest possible spilling / reloading points
|
||||
before register allocation. *)
|
||||
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Renaming of registers at reload points to split live ranges. *)
|
||||
|
||||
open Reg
|
||||
|
|
|
@ -10,8 +10,6 @@
|
|||
(* *)
|
||||
(***********************************************************************)
|
||||
|
||||
(* $Id$ *)
|
||||
|
||||
(* Renaming of registers at reload points to split live ranges. *)
|
||||
|
||||
val fundecl: Mach.fundecl -> Mach.fundecl
|
||||
|
|
|
@ -11,8 +11,6 @@
|
|||
# #
|
||||
#########################################################################
|
||||
|
||||
# $Id$
|
||||
|
||||
include ../config/Makefile
|
||||
|
||||
CC=$(NATIVECC)
|
||||
|
|
|
@ -11,8 +11,6 @@
|
|||
# #
|
||||
#########################################################################
|
||||
|
||||
# $Id$
|
||||
|
||||
include ../config/Makefile
|
||||
|
||||
CC=$(NATIVECC)
|
||||
|
|
|
@ -11,8 +11,6 @@
|
|||
/* */
|
||||
/***********************************************************************/
|
||||
|
||||
/* $Id$ */
|
||||
|
||||
/* Asm part of the runtime system, AMD64 processor */
|
||||
/* Must be preprocessed by cpp */
|
||||
|
||||
|
@ -493,7 +491,7 @@ LBL(110):
|
|||
popq C_ARG_2 /* arg 2: pc of raise */
|
||||
movq %rsp, C_ARG_3 /* arg 3: sp at raise */
|
||||
movq %r14, C_ARG_4 /* arg 4: sp of handler */
|
||||
/* PR#5700: thanks to popq above, stack is now 16-aligned */
|
||||
/* PR#5700: thanks to popq above, stack is now 16-aligned */
|
||||
PREPARE_FOR_C_CALL /* no need to cleanup after */
|
||||
call GCALL(caml_stash_backtrace)
|
||||
movq %r12, %rax /* Recover exception bucket */
|
||||
|
|
|
@ -11,8 +11,6 @@
|
|||
;* *
|
||||
;***********************************************************************
|
||||
|
||||
; $Id$
|
||||
|
||||
; Asm part of the runtime system, AMD64 processor, Intel syntax
|
||||
|
||||
; Notes on Win64 calling conventions:
|
||||
|
|
|
@ -12,8 +12,6 @@
|
|||
/* */
|
||||
/***********************************************************************/
|
||||
|
||||
/* $Id$ */
|
||||
|
||||
/* Asm part of the runtime system, ARM processor */
|
||||
/* Must be preprocessed by cpp */
|
||||
|
||||
|
|
|
@ -11,8 +11,6 @@
|
|||
/* */
|
||||
/***********************************************************************/
|
||||
|
||||
/* $Id$ */
|
||||
|
||||
/* Stack backtrace for uncaught exceptions */
|
||||
|
||||
#include <stdio.h>
|
||||
|
|
|
@ -11,8 +11,6 @@
|
|||
/* */
|
||||
/***********************************************************************/
|
||||
|
||||
/* $Id$ */
|
||||
|
||||
/* Raising exceptions from C. */
|
||||
|
||||
#include <signal.h>
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue