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gambatte/test/hwtests/tima
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sinamas 7f31aca5c2 verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
..
tc00_1stopstart_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_1stopstart_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_1stopstart_ff_tma_3_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_1stopstart_offset1_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_1stopstart_offset1_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_1stopstart_offset1_ff_tma_3_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_1stopstart_offset2_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_1stopstart_offset2_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_1stopstart_offset2_ff_tma_3_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_fe_ff_1_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_fe_ff_2_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_ff_tma_3_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_irq_ds_1_cgb04c_outE0.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_ds_2_cgb04c_outE4.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_ifw_1_dmg08_cgb04c_outE4.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_ifw_2_dmg08_cgb04c_outE0.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_ifw_ds_1_cgb04c_outE4.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_ifw_ds_2_cgb04c_outE0.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_late_retrigger_1_dmg08_cgb04c_outE4.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_late_retrigger_2_dmg08_outE4_cgb04c_outE0.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_late_retrigger_3_dmg08_cgb04c_outE0.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_late_retrigger_ds_1_cgb04c_outE4.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_irq_late_retrigger_ds_2_cgb04c_outE0.asm
libgambatte: irq timing detail re work
2019-03-25 23:31:04 +01:00
tc00_late_stop_inc_1_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_late_stop_inc_2_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_late_stop_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_late_stop_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_late_stop_of_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_late_stop_of_2_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_start_1_cgb04c_outF0.asm
hwtests: indicate cgb revision tested.
2015-03-23 02:19:55 +01:00
tc00_start_2_cgb04c_outF1.asm
hwtests: indicate cgb revision tested.
2015-03-23 02:19:55 +01:00
tc00_start_3_dmg08_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_start_4_dmg08_outF1.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_tc01_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_tc01_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_tc01_ff_tma_3_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_tc01_late_tc00_of_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc00_tc01_late_tc00_of_2_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_ff_tma_3_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset1_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset1_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset1_ff_tma_3_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset1_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset1_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset2_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset2_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset2_ff_tma_3_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset2_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset2_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset3_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset3_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset3_ff_tma_3_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset3_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_1stopstart_offset3_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_fe_ff_1_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_fe_ff_2_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_ff_tma_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_ff_tma_2_dmg08_cgb04c_out00.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_ff_tma_3_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_stop_inc_1_dmg08_cgb04c_outFD.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_stop_inc_2_dmg08_cgb04c_outFE.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_stop_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_stop_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_stop_of_1_dmg08_cgb04c_outFF.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_stop_of_2_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tima_inc_1_dmg08_cgb04c_out11.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tima_inc_2_dmg08_cgb04c_out10.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tima_irq_1_dmg08_cgb04c_outE0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tima_irq_2_dmg08_cgb04c_outE4.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tima_tma_1_dmg08_cgb04c_out11.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tima_tma_2_dmg08_cgb04c_outF1.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tima_tma_3_dmg08_cgb04c_out11.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tma_1_dmg08_cgb04c_out11.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_late_tma_2_dmg08_cgb04c_outF1.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_tma_next_1_dmg08_cgb04c_outF0.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00
tc01_tma_next_2_dmg08_cgb04c_outF1.asm
verify DMG TIMA test output
2019-03-31 23:42:46 +02:00