sinamas 01c9b09fc6 libgambatte: ds odd offset ly timing re work ...

Test LY timing at an apparent odd cycle offset in double speed mode
after multiple speed changes. Adjust accordingly.

Findings of note:
- In the event that LY is read at the boundary at which it gets
incremented, in an apparent window of one (single speed) cycle, the
resulting value appears to be LY & LY+1, where '&' denotes the bitwise
AND operation, and 'LY' is the value of LY prior to increment.

2019-10-01 00:16:34 +02:00

..

skew1_lyc98int_ly_count_ds_1_cgb04c_out99.asm

libgambatte: ds odd offset ly timing re work

2019-10-01 00:16:34 +02:00

skew1_lyc98int_ly_count_ds_2_cgb04c_out9A.asm

libgambatte: ds odd offset ly timing re work

2019-10-01 00:16:34 +02:00

skew1_lyc98int_ly_count_ds_3_cgb04c_out9A.asm

libgambatte: ds odd offset ly timing re work

2019-10-01 00:16:34 +02:00