165 lines
4.6 KiB
XML
165 lines
4.6 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE language SYSTEM "language.dtd">
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<language _name="VHDL" version="1.0" _section="Sources" mimetypes="text/x-vhdl">
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<line-comment _name = "Line Comment" style= "Comment">
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<start-regex>--</start-regex>
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</line-comment>
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<string _name = "String" style = "String" end-at-line-end = "TRUE">
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<start-regex>"</start-regex>
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<end-regex>"</end-regex>
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</string>
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<pattern-item _name = "Character Constant" style = "String">
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<regex>'.'</regex>
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</pattern-item>
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<keyword-list _name = "Keyword" style = "Keyword" case-sensitive="FALSE">
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<keyword>access</keyword>
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<keyword>after</keyword>
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<keyword>alias</keyword>
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<keyword>all</keyword>
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<keyword>architecture</keyword>
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<keyword>array</keyword>
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<keyword>assert</keyword>
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<keyword>attribute</keyword>
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<keyword>begin</keyword>
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<keyword>block</keyword>
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<keyword>body</keyword>
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<keyword>buffer</keyword>
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<keyword>bus</keyword>
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<keyword>case</keyword>
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<keyword>component</keyword>
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<keyword>configuration</keyword>
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<keyword>constant</keyword>
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<keyword>disconnect</keyword>
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<keyword>downto</keyword>
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<keyword>else</keyword>
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<keyword>elsif</keyword>
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<keyword>end</keyword>
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<keyword>entity</keyword>
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<keyword>exit</keyword>
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<keyword>file</keyword>
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<keyword>for</keyword>
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<keyword>function</keyword>
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<keyword>generate</keyword>
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<keyword>generic</keyword>
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<keyword>group</keyword>
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<keyword>guarded</keyword>
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<keyword>if</keyword>
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<keyword>impure</keyword>
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<keyword>in</keyword>
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<keyword>inertial</keyword>
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<keyword>inout</keyword>
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<keyword>is</keyword>
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<keyword>label</keyword>
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<keyword>library</keyword>
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<keyword>linkage</keyword>
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<keyword>literal</keyword>
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<keyword>loop</keyword>
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<keyword>map</keyword>
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<keyword>new</keyword>
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<keyword>next</keyword>
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<keyword>null</keyword>
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<keyword>of</keyword>
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<keyword>on</keyword>
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<keyword>open</keyword>
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<keyword>others</keyword>
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<keyword>out</keyword>
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<keyword>package</keyword>
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<keyword>port</keyword>
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<keyword>postponed</keyword>
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<keyword>procedure</keyword>
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<keyword>process</keyword>
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<keyword>pure</keyword>
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<keyword>range</keyword>
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<keyword>record</keyword>
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<keyword>register</keyword>
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<keyword>reject</keyword>
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<keyword>report</keyword>
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<keyword>return</keyword>
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<keyword>select</keyword>
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<keyword>severity</keyword>
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<keyword>signal</keyword>
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<keyword>shared</keyword>
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<keyword>subtype</keyword>
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<keyword>then</keyword>
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<keyword>to</keyword>
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<keyword>transport</keyword>
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<keyword>type</keyword>
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<keyword>unaffected</keyword>
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<keyword>units</keyword>
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<keyword>until</keyword>
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<keyword>use</keyword>
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<keyword>variable</keyword>
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<keyword>wait</keyword>
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<keyword>when</keyword>
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<keyword>while</keyword>
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<keyword>with</keyword>
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<keyword>note</keyword>
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<keyword>warning</keyword>
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<keyword>error</keyword>
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<keyword>failure</keyword>
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<keyword>and</keyword>
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<keyword>nand</keyword>
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<keyword>or</keyword>
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<keyword>nor</keyword>
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<keyword>xor</keyword>
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<keyword>xnor</keyword>
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<keyword>rol</keyword>
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<keyword>ror</keyword>
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<keyword>sla</keyword>
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<keyword>sll</keyword>
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<keyword>sra</keyword>
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<keyword>srl</keyword>
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<keyword>mod</keyword>
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<keyword>rem</keyword>
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<keyword>abs</keyword>
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<keyword>not</keyword>
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</keyword-list>
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<keyword-list _name = "Type" style = "Data Type" case-sensitive="FALSE">
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<keyword>bit</keyword>
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<keyword>bit_vector</keyword>
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<keyword>character</keyword>
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<keyword>boolean</keyword>
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<keyword>integer</keyword>
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<keyword>real</keyword>
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<keyword>time</keyword>
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<keyword>string</keyword>
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<keyword>severity_level</keyword>
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<keyword>positive</keyword>
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<keyword>natural</keyword>
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<keyword>signed</keyword>
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<keyword>unsigned</keyword>
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<keyword>line</keyword>
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<keyword>text</keyword>
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<keyword>std_logc</keyword>
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<keyword>std_logic_vector</keyword>
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<keyword>std_ulogic</keyword>
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<keyword>std_ulogic_vector</keyword>
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<keyword>qsim_state</keyword>
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<keyword>qsim_state_vector</keyword>
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<keyword>qsim_12state</keyword>
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<keyword>qsim_12state_vector</keyword>
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<keyword>qsim_strength</keyword>
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<keyword>mux_bit</keyword>
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<keyword>mux_vectory</keyword>
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<keyword>reg_bit</keyword>
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<keyword>reg_vector</keyword>
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<keyword>wor_bit</keyword>
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<keyword>wor_vector</keyword>
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</keyword-list>
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<pattern-item _name = "Number" style = "Decimal">
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<regex>\b[0-9]+(\b|\.|\.[0-9]*\b)</regex>
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</pattern-item>
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<keyword-list _name = "True and False" style = "Specials" case-sensitive="FALSE">
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<keyword>true</keyword>
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<keyword>false</keyword>
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</keyword-list>
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</language>
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