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Add more QSV CPUIDs

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This commit is contained in:
palana 2015-09-21 15:28:08 +02:00
parent 46e9df4f7f
commit d3d3edd40b
2 changed files with 57 additions and 13 deletions
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44
QSVHelper/QSVHelper.cpp
View File

@ -38,9 +38,9 @@ namespace {
enum qsv_cpu_platform enum qsv_cpu_platform
{ {
QSV_CPU_PLATFORM_UNKNOWN, QSV_CPU_PLATFORM_UNKNOWN,
QSV_CPU_PLATFORM_SNB = 1 << 0, QSV_CPU_PLATFORM_SNB_BNL = 1 << 0,
QSV_CPU_PLATFORM_IVB = 1 << 1, QSV_CPU_PLATFORM_IVB_SLM_CHT = 1 << 1,
QSV_CPU_PLATFORM_HSW = 1 << 2, QSV_CPU_PLATFORM_HSW = 1 << 2,
}; };
qsv_cpu_platform qsv_get_cpu_platform() qsv_cpu_platform qsv_get_cpu_platform()
@ -68,15 +68,35 @@ namespace {
switch (model) switch (model)
{ {
case 0x1C:
case 0x26:
case 0x27:
case 0x35:
case 0x36:
//BNL
case 0x2a: case 0x2a:
case 0x2d: case 0x2d:
return QSV_CPU_PLATFORM_SNB; //SNB
return QSV_CPU_PLATFORM_SNB_BNL;
case 0x3a: case 0x3a:
case 0x3e: case 0x3e:
return QSV_CPU_PLATFORM_IVB; //IVB
case 0x37:
case 0x4A:
case 0x4D:
case 0x5A:
case 0x5D:
//SLM
case 0x4C:
//CHT
return QSV_CPU_PLATFORM_IVB_SLM_CHT;
case 0x3c: case 0x3c:
case 0x3f:
case 0x45: case 0x45:
case 0x46: case 0x46:
return QSV_CPU_PLATFORM_HSW; return QSV_CPU_PLATFORM_HSW;
@ -92,13 +112,13 @@ namespace {
mfxVersion version; mfxVersion version;
int platforms; int platforms;
} valid_impl[] = { } valid_impl[] = {
{ MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D11, {8, 1}, QSV_CPU_PLATFORM_IVB | QSV_CPU_PLATFORM_HSW }, { MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D11, {8, 1}, QSV_CPU_PLATFORM_IVB_SLM_CHT | QSV_CPU_PLATFORM_HSW },
{ MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D9, {8, 1}, QSV_CPU_PLATFORM_IVB | QSV_CPU_PLATFORM_HSW }, //Ivy Bridge+ with non-functional D3D11 support? { MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D9, {8, 1}, QSV_CPU_PLATFORM_IVB_SLM_CHT | QSV_CPU_PLATFORM_HSW }, //Ivy Bridge+ with non-functional D3D11 support?
{ MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D11, {7, 1}, QSV_CPU_PLATFORM_IVB | QSV_CPU_PLATFORM_HSW }, { MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D11, {7, 1}, QSV_CPU_PLATFORM_IVB_SLM_CHT | QSV_CPU_PLATFORM_HSW },
{ MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D9, {7, 1}, QSV_CPU_PLATFORM_IVB | QSV_CPU_PLATFORM_HSW }, //Ivy Bridge+ with non-functional D3D11 support? { MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D9, {7, 1}, QSV_CPU_PLATFORM_IVB_SLM_CHT | QSV_CPU_PLATFORM_HSW }, //Ivy Bridge+ with non-functional D3D11 support?
{ MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D11, {6, 1}, QSV_CPU_PLATFORM_IVB | QSV_CPU_PLATFORM_HSW }, { MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D11, {6, 1}, QSV_CPU_PLATFORM_IVB_SLM_CHT | QSV_CPU_PLATFORM_HSW },
{ MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D9, {6, 1}, QSV_CPU_PLATFORM_IVB | QSV_CPU_PLATFORM_HSW }, //Ivy Bridge+ with non-functional D3D11 support? { MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D9, {6, 1}, QSV_CPU_PLATFORM_IVB_SLM_CHT | QSV_CPU_PLATFORM_HSW }, //Ivy Bridge+ with non-functional D3D11 support?
{ MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D9, {4, 1}, QSV_CPU_PLATFORM_IVB | QSV_CPU_PLATFORM_HSW | QSV_CPU_PLATFORM_SNB }, //Sandy Bridge { MFX_IMPL_HARDWARE_ANY, MFX_IMPL_VIA_D3D9, {4, 1}, QSV_CPU_PLATFORM_IVB_SLM_CHT | QSV_CPU_PLATFORM_HSW | QSV_CPU_PLATFORM_SNB_BNL }, //Sandy Bridge
}; };
std::wofstream log_file; std::wofstream log_file;

26
Source/Encoder_QSV.cpp
View File

@ -181,9 +181,12 @@ namespace
enum qsv_cpu_platform enum qsv_cpu_platform
{ {
QSV_CPU_PLATFORM_UNKNOWN, QSV_CPU_PLATFORM_UNKNOWN,
QSV_CPU_PLATFORM_BNL,
QSV_CPU_PLATFORM_SNB, QSV_CPU_PLATFORM_SNB,
QSV_CPU_PLATFORM_IVB, QSV_CPU_PLATFORM_IVB,
QSV_CPU_PLATFORM_HSW QSV_CPU_PLATFORM_SLM,
QSV_CPU_PLATFORM_CHT,
QSV_CPU_PLATFORM_HSW,
}; };
qsv_cpu_platform qsv_get_cpu_platform() qsv_cpu_platform qsv_get_cpu_platform()
@ -211,6 +214,13 @@ namespace
switch (model) switch (model)
{ {
case 0x1C:
case 0x26:
case 0x27:
case 0x35:
case 0x36:
return QSV_CPU_PLATFORM_BNL;
case 0x2a: case 0x2a:
case 0x2d: case 0x2d:
return QSV_CPU_PLATFORM_SNB; return QSV_CPU_PLATFORM_SNB;
@ -219,7 +229,18 @@ namespace
case 0x3e: case 0x3e:
return QSV_CPU_PLATFORM_IVB; return QSV_CPU_PLATFORM_IVB;
case 0x37:
case 0x4A:
case 0x4D:
case 0x5A:
case 0x5D:
return QSV_CPU_PLATFORM_SLM;
case 0x4C:
return QSV_CPU_PLATFORM_CHT;
case 0x3c: case 0x3c:
case 0x3f:
case 0x45: case 0x45:
case 0x46: case 0x46:
return QSV_CPU_PLATFORM_HSW; return QSV_CPU_PLATFORM_HSW;
@ -364,8 +385,11 @@ bool IsKnownQSVCPUPlatform()
static qsv_cpu_platform plat = qsv_get_cpu_platform(); static qsv_cpu_platform plat = qsv_get_cpu_platform();
switch (plat) switch (plat)
{ {
case QSV_CPU_PLATFORM_BNL:
case QSV_CPU_PLATFORM_SNB: case QSV_CPU_PLATFORM_SNB:
case QSV_CPU_PLATFORM_IVB: case QSV_CPU_PLATFORM_IVB:
case QSV_CPU_PLATFORM_SLM:
case QSV_CPU_PLATFORM_CHT:
case QSV_CPU_PLATFORM_HSW: case QSV_CPU_PLATFORM_HSW:
return true; return true;
} }