451 lines
14 KiB
C
451 lines
14 KiB
C
**************************************************************************
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* *
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* THE X-UNIT SYSTEM SPECIFIC EQUATES *
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* *
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**************************************************************************
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*
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*MACHINE TIMINGS
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*
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MACHINE_CYCLE .EQU 100 ;NUMBER OF nanoSECONDS PER MACHINE CYCLE on the 34020:
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; 32MHz = 132 ns
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; 40MHz = 100 ns
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MICRO_SECOND .EQU 1000/MACHINE_CYCLE ;MACHINE CYCLES PER microSECOND
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*
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*GENERAL SYSTEM EQUATES
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*
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*
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*PIXBLT STUFF
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PXSIZE .set 8
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SCRN_PTCH .set 512*PXSIZE
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CONV_PTCH .SET 13
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PLANEMSK .set 0
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INI_CFG .set 1108h
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INI_CTRL .set 0
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.IF WIDESCREEN
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SCREEN_WIDTH .EQU 512 ;SCREEN WIDTH IN PIXELS
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.ELSE
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SCREEN_WIDTH .EQU 400 ;SCREEN WIDTH IN PIXELS
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.ENDIF
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SCREEN_HEIGHT .EQU 254 ;SCREEN LENGTH IN PIXELS NEW
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*
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*SYSTEM Z MEMORY MAP
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*
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SCRATCH .SET 20000000h ;START OF SCRATCH
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CMOS .EQU 0a0440000h ;START OF CMOS RAM
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SCREEN .SET 00h ;START OF SCREEN MEMORY
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SCRNE .SET 0200000h ;END OF SCREEN+1
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PSCREEN .SET 800000h ;START OF PALETTE SCREEN MEMORY
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SCRATCH_END .EQU 20800000H ;END OF SCRATCH+1
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STCKST .SET 207ffff0h ;TOP OF STACK
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COLRAM .SET 0a0800000H ;COLOR RAM B0-B4 BLU, B5-B9 GRN, B10-B14 RED
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PALSIZE .SET 02000H ;PHYSICAL SIZE OF A PALETTE IN COLOR RAM
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*
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*USEFUL SYSTEM ADDRESSES
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*
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ROM .SET 20800000h ;PROGRAM ROM
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SWITCH .SET 60c00000h ;I/O (JAMMA CONNECTOR AND WIRED INPUTS)
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SWITCH2 .SET 60c00020H ;I/O (WIRED INPUTS AND DIP SWITCHES)
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COINS .SET 60c00040H
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DIPSWITCH .EQU 60c00060H ;DIP SWITCHES FOR X UNIT
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SOUND .SET 60c00080h ;SOUND I/O (B0-B7 = SOUND#)
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; B8 = RESET (0 EN)
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COIN_COUNTERS .EQU 60c000a0H ;COIN COUNTER DRIVERS
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WDOG_BONE .EQU 60c000c0H ;ACCESS HERE TO FEED THE DOG
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A2D_PORT .EQU 80800000H ;A/D PORT
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AUX_PORT .EQU 060C00080H ;AUXILLARY PORT
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IROM .SET 0f8000000h ;IMAGE ROM (assuming 4Mbit parts, 16MB total)
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;IROM .SET 0f0000000h ;IMAGE ROM (assuming 8Mbit parts, 32MB total)
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CMAPSEL .SET 0C0800080h ;COLOR MAP SELECT (0-15)
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UART .SET 80c00000h ;UART (8 long word registers)
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SYSCTRL0 .SET 40800000H ;SYSTEM CONTROL LATCH 0
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SYSCTRL1 .SET 40C00000H ;SYSTEM CONTROL LATCH 1
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SECCHIP .set 60000000h ;security register
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INT_REG .set 60400000h ;interrupt register
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RST_REG .set 60800000h ;reset register (bit 0 only)
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*
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* SYSCTRL0 bit 3 bit 2 bit 1 bit 0
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*
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* if set: VECTORS FROM ENABLE CMOS WRITE PROTECT WRITE PROTECT
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* DRAM WRITE BANK 1 HI BANK 1 LO
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*
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*
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* SYSCTRL1 bit 3 bit 2 bit 1 bit 0
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*
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* if set: DMA BANK 1 LED IS ON I/O RESET DMA ENABLED
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*
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*
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RAMVECTS .equ 8 ;use RAM VECTORS (not ROM)
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CMOSENAB .equ 4 ;enable CMOS
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WRPROTHI .equ 2 ;Write Protect Hi half of DRAM Bank 1
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WRPROTLO .equ 1 ;Write Protect Lo half of DRAM Bank 1
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DMABANK1 .equ 8 ;Select Hi BANK of IMAGE ROM (for DMA)
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LED_ON .equ 4 ;Turn on LED
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SND_RESET .equ 2 ;Reset Sound Board and PIC chip
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DMAENAB .equ 1 ;Enable DMA
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SYSCINIT .equ (DMAENAB<<8)+RAMVECTS ; for XUNIT
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;SYSCINIT .equ (DMAENAB<<8)+RAMVECTS+WRPROTHI ; for XUNIT
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SYSC_COLD .EQU 0 ;System control register upon cold start
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.IF UART
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LINT2_INTS .EQU 4 ;LINT2 interrupts, with UART
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.ELSE
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LINT2_INTS .EQU 0 ;LINT2 interrupts, without UART
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.ENDIF
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*
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*UART Equates
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*
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UART_CSR .EQU 20H ;UART Clock Select Register
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UART_CR .EQU 40H ;UART Control Register
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UART_THR .EQU 60H ;UART Transmit Hold Register
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UART_ACR .EQU 80H ;UART Auxiliary Control Register
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UART_IMR .EQU 0A0H ;UART Interrupt Mask Register
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*
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AUTOERAS .EQU 10H
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OBJPALET .EQU 20H
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*COIN COUNTER EQUATES ???HELP???
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LEFT_COIN .EQU 01H ;LEFT COIN MASK
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RIGHT_COIN .EQU 02H ;RIGHT COIN MASK
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*EQUATES FOR READING SOUND BOARD IRQ REQUEST LINE
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B_WDOG .EQU 30 ;(L) FOR WATCHDOG TRIGGERED
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B_A2D .EQU 0 ;(L) FOR CONVERSION COMPLETE
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B_SIRQ .EQU 2 ;BIT TO READ FOR SOUND IRQ LINE
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*
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*INTERRUPT CONSTANTS
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.IF NTSC
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ENDVBLNK .EQU 13H ;SCAN LINE TO END VERTICAL BLANKING
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HSINT .EQU 108+ENDVBLNK ;HALF SCREEN
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EOSINT .EQU 229+ENDVBLNK ;END OF SCREEN
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DIRQ2INT .EQU 210+ENDVBLNK ;JUST BEFORE EOS
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*SCOREINT .EQU 18+ENDVBLNK ;END OF SCORE AREA INTERRUPT
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.ELSE
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ENDVBLNK .EQU 14H ;SCAN LINE TO END VERTICAL BLANKING
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HSINT .EQU 135+ENDVBLNK ;HALF SCREEN
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EOSINT .EQU 254+ENDVBLNK ;END OF SCREEN
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DIRQ2INT .EQU 246+ENDVBLNK ;JUST BEFORE EOS
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*SCOREINT .EQU 18+ENDVBLNK ;END OF SCORE AREA INTERRUPT
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.ENDIF
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ERASELOC .EQU COLRAM + (03F0H*2) ;GAME AUTO ERASE COLOR LOCATION
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ERASECOL .EQU 03F3F3F3FH ;GAME AUTO ERASE COLOR #
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GNDERALOC .EQU COLRAM + (03E0H*2) ;GAME AUTO ERASE COLOR LOCATION
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GNDERACOL .EQU 03e3e3e3EH ;GAME AUTO ERASE COLOR #
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.if CENTER_SCREEN
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CENTER_XSHIFT .EQU 56
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.else
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CENTER_XSHIFT .EQU 0
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.endif
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BITMAP_OFFSET .EQU CENTER_XSHIFT*8
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PAGE0ADR .EQU [0,CENTER_XSHIFT] ;(1 dead, 44 score, 210 playfield)*2, 2 autoerase
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PAGE1ADR .EQU [SCRHGHT,CENTER_XSHIFT] ;SCRHGHT*8*512
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PAGE2ADR .EQU [512,CENTER_XSHIFT] ;Video page 2 XY address
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PAGE3ADR .EQU [768,CENTER_XSHIFT] ;Video page 3 XY address
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OFFSETVAL .set BITMAP_OFFSET
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TOGGLE_PAGE_XY .set [SCRHGHT,0]
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TOGGLE_PAGE_L .set SCRHGHT*SCRN_PTCH
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DPYSTRT0 .set BITMAP_OFFSET
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DPYSTRT1 .set (SCRHGHT*SCRN_PTCH)+BITMAP_OFFSET
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DPYSTRT2 .EQU (512*SCRN_PTCH)+BITMAP_OFFSET
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DPYSTRT3 .EQU (768*SCRN_PTCH)+BITMAP_OFFSET
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PAGE0E .EQU 0FE000h ;END OF PAGE0+1
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PAGE2_START .EQU 0200000H ;Start of video page 2
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PAGE2_END .EQU 02FFFFFH ;End of video page 2
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PAGE3_START .EQU 0300000H ;Start of video page 3
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PAGE3_END .EQU 03FFFFFH ;End of video page 3
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*
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*DMA STUFF
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*
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DMAREGS: .equ 0C08000C0h ;BOTTOM OF DMA REGISTERS FOR MMTM
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;BIT 15:
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;1=START DMA (WRITE)
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;0=STOP DMA (WRITE)
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;1=DMA BUSY (READ)
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;0=DMA IDLE (READ)
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;DMAOFFST: .EQU 0C0800000h ;DMA OFFSET REGISTER
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;DMACTRL: .equ 0C0800010h ;DMA CONTROL REGISTER
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;DMASAGL: .equ 0C0800020h ;DMA DATA STARTING ADDRESS LOW 16 BITS
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;DMASAGH: .equ 0C0800030h ;DMA DATA STARTING ADDRESS HIGH 16 BITS
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;DMAHORIZ: .equ 0C0800040h ;DMA DESTINATION, X COORDINATE
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;DMAVERT: .equ 0C0800050h ;DMA DESTINATION, Y COORDINATE
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;DMAHSIZE: .equ 0C0800060h ;DMA DESTINATION, X SIZE
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;DMAVSIZE: .equ 0C0800070h ;DMA DESTINATION, Y SIZE
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;DMACMAP: .equ 0C0800080h ;DMA COLOR MAP SELECT
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;DMACONST: .equ 0C0800090h ;DMA CONSTANT COLOR SUBSTITUTE
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;DMAXSCL: .equ 0C08000A0h ;DMA X SCALE REG
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;DMAYSCL: .equ 0C08000B0h ;DMA Y SCALE REG
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;DMATPLFT: .equ 0C08000C0h ;DMA TOP LEFT WINDOW BORDER
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;DMARTBOT: .equ 0C08000D0h ;DMA RT BOTTOM WINDOW BORDER
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;DMACONFIG: .equ 0C08000E0h ;DMA CONFIG REGISTER
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; ALL DMA REGS ARE 32 BITS!!!
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DMAOFFCTL: .EQU 0C0800000h ;DMA OFFSET & CONTROL REGISTERS
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DMASAG: .equ 0C0800020h ;DMA DATA STARTING ADDRESS
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DMAHV: .equ 0C0800040h ;DMA DESTINATION, XY COORDINATE
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DMAHVSIZE: .equ 0C0800060h ;DMA DESTINATION, XY SIZE
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DMACMAPCON: .equ 0C0800080h ;DMA COLOR MAP SELECT, CONST
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DMAXYSCL: .equ 0C08000A0h ;DMA XY SCALE REG
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DMAWINDOW: .equ 0C08000C0h ;DMA BOT:TOP or RT:LEFT WINDOW BORDER
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DMACONFIG: .equ 0C08000E0h ;DMA CONFIG REGISTER
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DMAGOREG .equ 0C0C00000h ; for read/write of DMA GO BIT ONLY (in bit 31)
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; NOTE: trashes offset & control regs on a write.
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* LAYOUT OF DMA CONTROL REGISTER
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DMAWZ .set 8001h ; Bit 0 write zero data
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DMAWNZ .set 8002h ; Bit 1 write non-zero data
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DMACZ .set 8004h ; Bit 2 subst zero data with constant
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DMACNZ .set 8008h ; Bit 3 subst non-zero data with constant
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DMAWAL .SET 8003h ; WRITE BOTH ZERO & NON-ZERO DATA
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DMACAL .SET 800ch ; WRITE CONSTANT ON BOTH ZERO & NON-ZERO DATA
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DMAHFL .set 0010h ; Bit 4 Horz flip
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DMAVFL .set 0020h ; Bit 5 Vert flip
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DMACLP .set 0040h ; Bit 6 Clip using UDLR method (0=offset method)
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DMACMP .set 0080h ; Bit 7 Zero Compression on
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DMALDX .set 0300h ; Bits 8-9 Leading Zero Multiplier (0-3 = 1x,2x,4x,8x)
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DMATRX .set 0c00h ; Bits 10-11 Trailing Zero Multiplier (0-3 = 1x,2x,4x,8x)
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DMABPP .set 7000h ; Bits 12-14 Bits Per Pixel (1-7, 0=8)
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DMAGO .set 8000h ; Bit 15 DMA Go/Halt
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; (one '0' write halts DMA,
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; two '0' writes kills xfer,
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; one '1' write restarts/starts)
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* LAYOUT OF DMA CONFIG REGISTER
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DMAWIN .set 200000h ; Bit 5 (0 = rt/lft, 1 = top/bot)
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DMACF4 .SET 100000H ; BIT 4 TIMING PARAMETER
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* LAYOUT OF IMAGE HEADER NEW
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ICTRL .EQU 0H
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ISIZE .equ 10h
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ISIZEX .EQU 10h
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ISIZEY .EQU 20H
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ISAG .equ 30h
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IANIOFF .equ 50H
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IANIOFFX .EQU 50H
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IANIOFFY .EQU 60H
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ICMAP .equ -20H
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ICBOX .equ 90H
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ICBOXSIZ .equ 0A0H
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IHDRSIZ equ 70h
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ZM .set 1 ;Z MINUS MULTIPLIER
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ZP .set 010000h ;Z PLUS MULTIPLIER
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*
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*SOUND PROCESSOR EQUATES
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NINT .EQU 0800H ;SOUND NON-INTERRUPTABLE ???HELP???
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*------- Register names for TMS34010 assembly language functions -------
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*-----------------------------------------------------------------------
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* Define names of I/O registers
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*-----------------------------------------------------------------------
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VESYNC .set 0C0000000h
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HESYNC .set 0C0000010h
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VEBLNK .set 0C0000020h
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HEBLNK .set 0C0000030h
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VSBLNK .set 0C0000040h
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HSBLNK .set 0C0000050h
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VTOTAL .set 0C0000060h
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HTOTAL .set 0C0000070h
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DPYCTL .set 0C0000080h
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DPYSTRT .set 0C0000090h
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DPYINT .set 0C00000A0h
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CONTROL .set 0C00000B0h
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HSTDATA .set 0C00000C0h
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HSTADRL .set 0C00000D0h
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HSTADRH .set 0C00000E0h
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HSTCTLL .set 0C00000F0h
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HSTCTLH .set 0C0000100h
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INTENB .set 0C0000110h
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INTPEND .set 0C0000120h
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CONVSP .set 0C0000130h
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CONVDP .set 0C0000140h
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PSIZE .set 0C0000150h
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PMASKL .set 0C0000160h
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PMASKH .set 0C0000170h
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CONVMP .set 0C0000180h
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CONFIG .set 0C00001a0h
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DPYTAP .set 0C00001b0h
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* I/O register locations 23-27 are reserved for future expansion
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VCOUNT .set 0C00001C0h
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HCOUNT .set 0C00001D0h
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DPYADR .set 0C00001E0h
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REFADR .set 0C00001F0h
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*
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DPYMSK .set 0C00002E0h ; replaces DPYTAP
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DPYST .set 0C0000200h ; replaces DPYSTRT
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DPYNX .SET 0C0000220H ; replaces DPYADR
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X .set 1
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Y .set 010000h
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W .SET 0
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L .set 1
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* Declarations for condition codes in Macros
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GT .set 'GT'
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GE .set 'GE'
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LT .set 'LT'
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LE .set 'LE'
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EQ .set 'EQ'
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NE .set 'NE'
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Z .set 'Z'
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NZ .set 'NZ'
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NC .set 'NC'
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UC .set 'UC'
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N .set 'N'
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*-----------------------------------------------------------------------
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* Masks for I/O register fields:
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*-----------------------------------------------------------------------
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* STATUS BIT MASKS
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CBIT .EQU 40000000H
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* DISPLAY CONTROL REGISTER BIT DEFINITIONS
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HSD .set 01h ; Horizontal Sync Direction
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VSD .set 02h ; Vertical Sync Direction
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CSD .set 04h ; Composite Sync Direction
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CVD .set 08h ; Composite Video Disable
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SSV .set 040h ; Midline reload enable
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VCE .set 080h ; Video capture enable
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CST .set 0800h ; CPU serial register transfer enable
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SRE .set 01000h ; Screen Refresh Enable
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NIL .set 04000h ; Non-InterLaced video enable
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ENV .set 08000h ; ENable Video
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*BIT POSITIONS IN DISPLAY CONTROL
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B_CST .SET 11 ; BIT TO ENABLE CSTs
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B_SSV .SET 6 ; BIT TO ENABLE SRTs
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* BIT FIELDS WITHIN CONTROL REGISTER
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CD .set 08000h ;Mask for Cache Dis bit in CONTROL
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PPOP .set 07C00h ;Mask for Pix Proc OPer in CONTROL
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PBH .set 0200h ;Mask for PBH bit in CONTROL
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PBV .set 0100h ;Mask for PBV bit in CONTROL
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WIN .set 0C0h ;Mask for Window field in CONTROL
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T .set 020h ;Mask for Transparency field in CONTROL
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TMD .set 3 ;Mask for Transparency MODE in CONTROL
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;old RR .set 018h ;Mask for dram Refresh Rate bit in CONFIG
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;old RM .set 04h ;Mask for dram Refresh Mode bit in CONFIG
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* BITS WITHIN INTPEND AND INTENB
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WVP .set 0800h ;Mask for Window Violation in INTPEND
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DIE .set 0400h ;Mask for Disp Int in INTPEND
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HIE .set 0200h ;Mask for Host Int in INTPEND
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X2E .set 04h ;Mask for Ext Int 2 in INTPEND
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X1E .set 02h ;Mask for Ext Int 1 in INTPEND
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B_X1E .set 1 ;Bit Pos for Ext Int 1 in INTPEND
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* BIT POSITIONS IN INTPEND
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DIP .EQU 10 ;BIT TEST FOR DISPLAY INTERRUPT PENDING
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* FIELDS WITHIN HSTCTLL
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MSGIN .set 07h ; Message from Host to GSP
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INTIN_MSK .set 08h ; GSP can write 0 to this bit (ANDNI)
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INTIN_BIT .set 03h ; GSP can write 0 to this bit (ANDNI)
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INTOUT_MSK .set 080h ; GSP can write 1 to this bit (ORI)
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INTOUT_BIT .set 07h ; GSP can write 1 to this bit (ORI)
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* OPTIONS FOR WINDOW FIELD IN CONTROL REG
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*W0 (ANDNI) No writes inhibited, no interrupt
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W3 .set 0C0h ;inhibit writes outside window, no interrupt
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W2 .set 080h ;Int on attempt to write outside window.
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W1 .set 040h ;Inhibit all writes, Int on attempt to write within window
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*OPTIONS FOR PIXEL PROC OPERATIONS IN CONTROL REG
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* PPOP (ANDNI) replace
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P_AND .set 0400h
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P_ANDNOT .set 0800h
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P_ZERO .set 0C00h
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P_ORNOT .set 01000h
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P_XNOR .set 01400h
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P_NEG .set 01800h
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P_NOR .set 01C00h
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P_OR .set 02000h
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P_NOP .set 02400h
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P_XOR .set 02800h
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P_NOTAND .set 02C00h
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P_ONES .set 03000h
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P_NOTOR .set 03400h
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P_NAND .set 03800h
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P_NOT .set 03C00h
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P_ADD .set 04000h
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P_ADDS .set 04400h
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P_SUB .set 04800h
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P_SUBS .set 04C00h
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P_MAX .set 05000h
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P_MIN .set 05400h
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*-----------------------------------------------------------------------
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* Define special A- and B-file registers
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*-----------------------------------------------------------------------
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* Special A-file registers:
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***fp .set A13 ;Frame, param. stack
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***pstk .set A14 ;Parameter stack pointer
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***frame_pntr .set A14 ;Used by C Compiler
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* Special B-file registers:
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*
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* B FILE REGISTER GRAPHICS DEFINITIONS
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*
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***saddr .set B0
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***sptch .set B1
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***daddr .set B2
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***dptch .set B3
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***offset .set B4
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***wstart .set B5
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***wend .set B6
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***dydx .set B7
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***color0 .set B8
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***color1 .set B9
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***count .set B10
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***inc1 .set B11
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***inc2 .set B12
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***pattrn .set B13
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*
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SADDR .set B0 ;Source address register
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SPTCH .set B1 ;Source pitch register
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DADDR .set B2 ;Dest. address register
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DPTCH .set B3 ;Dest. pitch register
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OFFSET .set B4 ;XY offset register
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***WSTART .set B5 ;Window start register
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***WEND .set B6 ;Window end register
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DYDX .set B7 ;Delta X/delta Y register
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COLOR0 .set B8 ;Color 0 register
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COLOR1 .set B9 ;Color 1 register
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***COUNT .set B10
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***INC1 .set B11
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***INC2 .set B12
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***PATTRN .set B13
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