185 lines
5.3 KiB
Plaintext
185 lines
5.3 KiB
Plaintext
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*------- Register names for TMS34010 assembly language functions -------
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*-----------------------------------------------------------------------
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* Define special A- and B-file registers
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*-----------------------------------------------------------------------
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* Special A-file registers:
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***fp .set A13 ;Frame, param. stack
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***pstk .set A14 ;Parameter stack pointer
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***frame_pntr .set A14 ;Used by C Compiler
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* Special B-file registers:
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*
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* B FILE REGISTER GRAPHICS DEFINITIONS
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*
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***saddr .set B0
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***sptch .set B1
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daddr .set B2
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dptch .set B3
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offset .set B4
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***wstart .set B5
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***wend .set B6
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***dydx .set B7
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***color0 .set B8
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color1 .set B9
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***count .set B10
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***inc1 .set B11
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***inc2 .set B12
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***pattrn .set B13
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*
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SADDR .set B0 ;Source address register
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SPTCH .set B1 ;Source pitch register
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DADDR .set B2 ;Dest. address register
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DPTCH .set B3 ;Dest. pitch register
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OFFSET .set B4 ;XY offset register
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WSTART .set B5 ;Window start register
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WEND .set B6 ;Window end register
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DYDX .set B7 ;Delta X/delta Y register
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COLOR0 .set B8 ;Color 0 register
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COLOR1 .set B9 ;Color 1 register
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COUNT .set B10
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INC1 .set B11
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INC2 .set B12
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PATTRN .set B13
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*-----------------------------------------------------------------------
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* Define names of I/O registers
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*-----------------------------------------------------------------------
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HESYNC .set 0C0000000h
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HEBLNK .set 0C0000010h
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HSBLNK .set 0C0000020h
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HTOTAL .set 0C0000030h
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VESYNC .set 0C0000040h
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VEBLNK .set 0C0000050h
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VSBLNK .set 0C0000060h
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VTOTAL .set 0C0000070h
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DPYCTL .set 0C0000080h
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DPYSTRT .set 0C0000090h
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DPYINT .set 0C00000A0h
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CONTROL .set 0C00000B0h
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HSTDATA .set 0C00000C0h
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HSTADRL .set 0C00000D0h
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HSTADRH .set 0C00000E0h
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HSTCTLL .set 0C00000F0h
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HSTCTLH .set 0C0000100h
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INTENB .set 0C0000110h
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INTPEND .set 0C0000120h
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CONVSP .set 0C0000130h
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CONVDP .set 0C0000140h
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PSIZE .set 0C0000150h
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PMASK .set 0C0000160h
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* I/O register locations 23-27 are reserved for future expansion
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HCOUNT .set 0C00001C0h
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VCOUNT .set 0C00001D0h
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DPYADR .set 0C00001E0h
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REFCNT .set 0C00001F0h
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*
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hesync .set 0C0000000h
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heblnk .set 0C0000010h
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hsblnk .set 0C0000020h
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htotal .set 0C0000030h
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vesync .set 0C0000040h
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veblnk .set 0C0000050h
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vsblnk .set 0C0000060h
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vtotal .set 0C0000070h
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* Display and memory control registers
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dpyctl .set 0C0000080h
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dpystrt .set 0C0000090h
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dpyint .set 0C00000A0h
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control .set 0C00000B0h
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* Host interface registers
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hstdata .set 0C00000C0h
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hstadrl .set 0C00000D0h
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hstadrh .set 0C00000E0h
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hstctll .set 0C00000F0h
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hstctlh .set 0C0000100h
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* Interrupt control registers
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intenb .set 0C0000110h
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intpend .set 0C0000120h
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* Graphics I/O registers
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convsp .set 0C0000130h
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convdp .set 0C0000140h
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psize .set 0C0000150h
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pmask .set 0C0000160h
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*
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hcount .set 0C00001C0h
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vcount .set 0C00001D0h
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dpyadr .set 0C00001E0h
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refcnt .set 0C00001F0h
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X .set 1
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Y .set 010000h
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W .SET 0
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L .set 1
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*-----------------------------------------------------------------------
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* Masks for I/O register fields:
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*-----------------------------------------------------------------------
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* DISPLAY CONTROL REGISTER BIT DEFINITIONS
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HSD .set 01h ; Horizontal Sync Direction
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DUDATE .set 0000001111111100B ; display update (2-9)
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ORG .set 0400h ; ORiGin (1 = lower left; 0 = upper left)
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SRT .set 0800h ; Shift Reg Transfer enable
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SRE .set 01000h ; Screen Refresh Enable
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DXV .set 02000h ; Disable eXternal Video
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NIL .set 04000h ; Non-InterLaced video enable
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ENV .set 08000h ; ENable Video
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* BIT FIELDS WITHIN CONTROL REGISTER
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CD .set 08000h ;Mask for Cache Dis bit in CONTROL
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PPOP .set 07C00h ;Mask for Pix Proc OPer in CONTROL
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PBH .set 0200h ;Mask for PBH bit in CONTROL
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PBV .set 0100h ;Mask for PBV bit in CONTROL
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WIN .set 0C0h ;Mask for Window field in CONTROL
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T .set 020h ;Mask for Transparency field in CONTROL
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RR .set 018h ;Mask for dram Refresh Rate bit in CONTROL
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RM .set 04h ;Mask for dram Refresh Mode bit in CONTROL
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* BITS WITHIN INTPEND AND INTENB
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WVP .set 0800h ;Mask for Window Violation in INTPEND
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DIE .set 0400h ;Mask for Disp Int in INTPEND
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HIE .set 0200h ;Mask for Host Int in INTPEND
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X2E .set 04h ;Mask for Ext Int 2 in INTPEND
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X1E .set 02h ;Mask for Ext Int 1 in INTPEND
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* BIT POSITIONS IN INTPEND
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DIP .EQU 10 ;BIT TEST FOR DISPLAY INTERRUPT PENDING
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* FIELDS WITHIN HSTCTLL
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MSGIN .set 07h ; Message from Host to GSP
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INTIN_MSK .set 08h ; GSP can write 0 to this bit (ANDNI)
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INTIN_BIT .set 03h ; GSP can write 0 to this bit (ANDNI)
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INTOUT_MSK .set 080h ; GSP can write 1 to this bit (ORI)
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INTOUT_BIT .set 07h ; GSP can write 1 to this bit (ORI)
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* OPTIONS FOR WINDOW FIELD IN CONTROL REG
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*W0 (ANDNI) No writes inhibited, no interrupt
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W3 .set 0C0h ;inhibit writes outside window, no interrupt
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W2 .set 080h ;Inhibit all writes, Int on attempt to write within window
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W1 .set 040h ;Int on attempt to write outside window.
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*OPTIONS FOR PIXEL PROC OPERATIONS IN CONTROL REG
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* PPOP (ANDNI) replace
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P_AND .set 0400h
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P_ANDNOT .set 0800h
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P_ZERO .set 0C00h
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P_ORNOT .set 01000h
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P_XNOR .set 01400h
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P_NEG .set 01800h
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P_NOR .set 01C00h
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P_OR .set 02000h
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P_NOP .set 02400h
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P_XOR .set 02800h
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P_NOTAND .set 02C00h
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P_ONES .set 03000h
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P_NOTOR .set 03400h
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P_NAND .set 03800h
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P_NOT .set 03C00h
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P_ADD .set 04000h
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P_ADDS .set 04400h
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P_SUB .set 04800h
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P_SUBS .set 04C00h
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P_MAX .set 05000h
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P_MIN .set 05400h
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