314 lines
10 KiB
Plaintext
Executable File
314 lines
10 KiB
Plaintext
Executable File
*VUNIT.EQU
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*
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*COPYRIGHT (C) 1994 BY TV GAMES, INC.
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*ALL RIGHTS RESERVED
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*
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DEBUG .set 0 ;0 = NO DEBUG CODE
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PRINTER .set 0 ;1 = PRINTER IS AVAILABLE
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STATISTICS .set 0 ;1 = BOG OUT STATISTICS GENERATION
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CODE_CHECK .set 0 ;1 = LOCK ON CODE INTEGRITY ERROR
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;COMMP .set 1 ;1 = COMMUNICATION CODE ACTIVE
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;see also: COMM.EQU
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*----------------------------------------------------------------------------
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*MEMORY MAP
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*
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FASTRAM .set 0000000h ;PROGRAM RAM
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SCREEN .set 0900000h ;VIDEO SCREEN RAM (512 HORIZ X 1024 VERT)
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SCREEN0 .set 0900000h ;PAGE 0 3 HW STATES
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SCREEN1 .set 0940000h ;PAGE 1 PAL BITS 15-8, COL BITS 7-0
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CMOS .set 09C0000H ;MASK=0FF000000h, LEN = 02000h 4 SW STATES
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COLORAM .set 09E0000h ;32K X 24 BITS RGB 2 SW STATES
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WAVERAM .set 0A00000h ;WAVE RAM DMA ACCESSABLE 2D IMAGE STORE
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SND2 .set 09A0000h ;ONBOARD NEW SOUND PORT
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OUT1 .set 0996000h ;IDE
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SOUND .set 0995000h ;SOUND OUTPUT PORT
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DIPSW .set 0992000h ;DIP SWITCHES
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SWITCH1 .set 0991060h ;SWITCH INPUTS (bits 15-8)
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SWITCH2 .set 0991050h ;SWITCH INPUTS (bits 15-8)
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SWITCH3 .set 0991030h ;SWITCH INPUTS (bits 15-8)
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FASTRAM .set 0000000h ;FAST STATIC RAM
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*----------------------------------------------------------------------------
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*----------------------------------------------------------------------------
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*DMA CONTROL WORD
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*
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DITHER .set 02000h ;DITHER
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CLIPEN .set 01000h ;DO NOT CLIP THIS POLYGON
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ZS .set 00800h ;ZERO SUPRESS
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NZR .set 00400h ;NON-ZERO REPLACEMENT
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METHOD .set 00300h ;METHOD OF PLOTTING
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FASTCC .set 00200h ;FAST CONSTANT COLOR (NO IVs OR ADDR)
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TM .set 00100h ;TEXTURE MAPPING
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CC .set 00000h ;CONSTANT COLOR
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COLOR .set 000FFh ;COLOR FIELD
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*----------------------------------------------------------------------------
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*----------------------------------------------------------------------------
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* FIFO EQUATES
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*
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FIFO_STATUS .set 0980082h ;READ ANYTIME, GENERAL STATUS (4 BITS) (READ ONLY)
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FIFO_STATUS_FD_CRITICAL .set 08h ;FIFO DATA BUS IS BEING USED
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FIFO_STATUS_MAX_FLAG .set 04h ;FIFO IS MAXED OUT (NO ENTRIES LEFT)
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FIFO_STATUS_DMA_ACTIVE .set 02h ;DMA IS PLOTTING AN IMAGE TO THE SCREEN (even if no fifo used)
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FIFO_STATUS_FIFO_NEMPTY .set 01h ;FIFO IS NOT EMPTY
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FIFO_CONTROL .set 0980080h ;READ/WRITE CONTROL REGISTER 0
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FIFO_CONTROL_DMA_RUNSEL .set 08h ;(0) -> (1) ENABLES DMA TO RUN user should set to 1 on powerup, is 0 on powerup otherwise
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FIFO_CONTROL_COUNTER_LD .set 04h ;(0) -> (0) ENABLES USER TO LOAD # OF ENTIRES IN FIFO (mostly useless)
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FIFO_CONTROL_FIFO_RST .set 02h ;(1) -> (0) RESETS THE FIFO COUNTER (NOT FIFO) (set to 1)
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FIFO_CONTROL_RST_CT_CHN .set 01h ;(1) -> (0) CRT CONTROLLER RESET user should set to 0 on powerup
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FIFO_CONTROL_INIT .set FIFO_CONTROL_DMA_RUNSEL
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FIFO_CNTR .set 0980000h ;READ FIFO COUNTER 15-0
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FIFO_SIZE .set 0980041h ;WRITE MAX ENTRIES FOR FIFO (271 FOR 4k FIFO)
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FIFO_INC .set 0980083h ;READ THIS PERFORMS THE SAME FUNCTION AS FIFO
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; STATUS, BUT ALSO INCREMENTS THE FIFO ENTRIES
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FIFO_ADDR .set 0600000h ;WRITE
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*
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*THIS IS UNTESTED 7/13/93
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*to access the 'other' wave ram bank (for WRITING!!!)
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* 1) set FIFO_CONTROL_DMA_RUNSEL <- 0
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* 2) dma will not initiate another BLIT
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* 3) check the FIFO_STATUS_FD_CRITICAL in FIFO_STATUS
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* until == 0
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* 4) now able to update DMA_SETUP (DMA_WAVE_RAM_BANK)
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* 5) set FIFO_CONTROL_DMA_RUNSEL <- 1
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*
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*This method is also usable for opto counters.
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*
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*
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* DMA EQUATES
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*
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*
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DMA_SETUP .set 0980040h ;READ/WRITE A VERY IMPORTANT REGISTER
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DMA_WDVD_DISABLE .set 08000h ;0 0 LSI TESTING ALWAYS SET TO 0 (HW BACKDOOR)
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DMA_CHIP_TRISTATE .set 04000h ;0 0 LSI TESTING ALWAYS SET TO 0 (HW BACKDOOR)
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DMA_CHIP_DISABLE .set 02000h ;0 0 IF SET TO 1, CHIP LOCKUP ONLY UNDOABLE BY CHIP RESET
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DMA_TEST_TOGGLE .set 01000h ;0 0 LSI TESTING ALWAYS SET TO 0 (HW BACKDOOR)
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DMA_TEST_MODE .set 00800h ;0 0 LSI TESTING ALWAYS SET TO 0 (HW BACKDOOR)
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DMA_MODE_32 .set 00400h ;0 0 FUTURE EXPANSION ALWAYS SET TO 0
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DMA_FIFO_INC_DISABLE2 .set 00200h ;0 1 HW KLUDGE SEE MARK ALWAYS SET TO 1
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DMA_FIFO_INC_DISABLE .set 00100h ;0 0 HW KLUDGE TO DISABLE
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DMA_DITHER_PHASE .set 00080h ;0 0 (0 = EVEN ON, 1 = EVEN OFF)
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DMA_POLY_ABORT_DISABLE .set 00040h ;0 0 (1 == DISABLE THE BONEHEAD ABORTION, EX ALL NEG.))
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DMA_REVERSE_WRITE_DIS .set 00020h ;0 0 (1 == DISABLE THE FAST MATH REVERSE PLOTTING)
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DMA_NO_FIFO_BIT .set 00010h ;0 0 "DONT GRAB DATA FROM THE FIFO, DMA REGS ALREADY SETUP"
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DMA_WAVE_RAM_BANK .set 00008h ;0 0 FOR WRITING INTO THE BANK
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DMA_DMA_WRITE_PAGE .set 00004h ;0 0 WHICH PAGE TO PLOT (0 = 0, 1 = 1)
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DMA_ROW_TRANSFER_ENABLE .set 00002h ;0 0 SRT ENABLE (UNTESTED 7/13/93)
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DMA_VIDEO_PAG_DISPLAYED .set 00001h ;0 0 WHICH PAGE TO SCREEN (0 = 0, 1 = 1)
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DMA_SETUP_INIT .set DMA_FIFO_INC_DISABLE2
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;DMA_SETUP_INIT .set DMA_FIFO_INC_DISABLE2|DMA_NO_FIFO_BIT
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DMA_CTRL .set 0980000h ;DMA CONTROL
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DMA_CMAP .set 0980001h ;PALETTE NUMBER
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DMA_AX .set 0980002h ;BITMAP AX (BITS 15-0)
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DMA_AY .set 0980003h ;
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DMA_AZ .set 0980004h ;
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DMA_BX .set 0980005h ;BITMAP BX (BITS 15-0)
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DMA_BY .set 0980006h ;
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DMA_BZ .set 0980007h ;
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DMA_CX .set 0980008h ;BITMAP CX (BITS 15-0)
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DMA_CY .set 0980009h ;
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DMA_CZ .set 098000Ah ;
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DMA_DX .set 098000Bh ;BITMAP DX (BITS 15-0)
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DMA_DY .set 098000Ch ;
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DMA_DZ .set 098000Dh ;
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DMA_IVA .set 098000Eh ;SOURCE AY (BITS 15-8) AX (BITS 7-0)
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DMA_IVB .set 098000Fh ;SOURCE BY (BITS 15-8) BX (BITS 7-0)
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DMA_IVC .set 0980010h ;SOURCE CY (BITS 15-8) CX (BITS 7-0)
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DMA_IVD .set 0980011h ;SOURCE DY (BITS 15-8) DX (BITS 7-0)
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DMA_LINE .set 0980012h ;Y LINE OFFSET (BITS 14-0)
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*DMA_CTRL BITS
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DMA_DITHER .set 2000h ;DITHER
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DMA_CLIPEN .set 1000h ;CLIP ENABLE
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DMA_ZWRSUP .set 0800h ;ZWR SUPPRESS
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DMA_NZR .set 0400h ;NON ZERO REPLACE
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DMA_METH1 .set 0200h ;FAST CONSTANT COLORED
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DMA_METH0 .set 0100h ;TEXTURE MAP
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DMA_COLOR .set 00FFh ;COLOR FIELD
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*
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* CRT CONTROL REGISTERS
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*
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*
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CRT_VCNT .set 0980020h ;READ the vertical line count (bits 0-8)
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CRT_SETUP .set 0980020h ;WRITE CRT SETUP REGISTER
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CRT_HADDRINC .set 0980021h ;WRITE horizontal addr increment(bits 09-00) 01ff
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CRT_HBLKSTART .set 0980022h ;WRITE horizontal blank start (bits 09-00) 01fe
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CRT_HSYNCSTART .set 0980023h ;WRITE horizontal sync start (bits 09-00) 0226
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CRT_HSYNCEND .set 0980024h ;WRITE horizontal sync end (bits 09-00) 025e
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CRT_HBLKEND .set 0980025h ;WRITE horizontal blank end (bits 09-00) 029f
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CRT_HTTL .set 0980026h ;WRITE horizontal total (bits 09-00) 02a0
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CRT_VBLKSTART .set 0980027h ;WRITE vert blank start (bits 08-00) 018f
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CRT_SYNCSTART .set 0980028h ;WRITE sync start (bits 08-00) 0195
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CRT_SYNCEND .set 0980029h ;WRITE sync end (bits 08-00) 0198
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CRT_VBLK .set 098002Ah ;WRITE blank end (bits 08-00) 01b0
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CRT_VTTL .set 098002Bh ;WRITE vertical total (bits 08-00) 01b0
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CRT_SETUP_DIVIDE .set 8000h ;DIVIDE VIDCLK BY 2
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CRT_SETUP_CSYNCV .set 4000h ;CSYNC OUT ON VERT
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CRT_SETUP_CSYNCH .set 2000h ;CSYNC OUT ON HORZ
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CRT_SETUP_ISYNCV .set 1000h ;INVERT VSYNC
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CRT_SETUP_ISYNCH .set 0800h ;INVERT HSYNC
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CRT_SETUP_ICSYNC .set 0400h ;INVERT CSYNC
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CRT_SETUP_RESERVED .set 0200h ;RESERVED
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CRT_SETUP_DISP_INT_LN .set 01FFh ;MASK DISPLAY INT LINE
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CRT_SETUP_INIT .set 399|CRT_SETUP_CSYNCH
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*----------------------------------------------------------------------------
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*----------------------------------------------------------------------------
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* SYSTEM CONTROL FLAGS
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SYSCNTLR .set 0994000h ;this is the REAL LOCATION (8 bits only)
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.globl _SYSCNTL ;this is the SHADOW LOCATION
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LED_OFF .set 0000080h ;turn led off
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ATOD_RD .set 040h
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ATOD_WR .set 020h
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ATOD_MASK .set 060h
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ATOD_R .set 0993000h ;ATOD register
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WDOG .set 0008h ;WATCHDOG
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;
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;once every 1.6 seconds
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;worst case 1.2 seconds
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;
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GENERAL_WP .set 010h ;WRITE PROTECT VECTOR,IMAGE
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SND2_RESET .set 002h ;0 = RESET ONBOARD SOUND SYSTEM
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SYSCNTL_INIT .set 0FFh ;FIFO_RESET|FIFO_RETRANS|RUN_SELECT|ATOD_MASK|GENERAL_WP
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CMOS_WP_WORD .set 0995020h ;CMOS WRITE PROTECT WORD
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CMOS_WP .set 0C00h ;CMOS WP DISABLED (ON = 0)
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*----------------------------------------------------------------------------
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MINUS_CHAR .set '>'
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*----------------------------------------------------------------------------
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*SWITCH EQUATES
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*
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*SWITCH = (SWITCH1 >> 16) | (SWITCH3 << 16)
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*
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*
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SW_COIN1 .set 00000001h
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SW_COIN2 .set 00000002h
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SW_START .set 00000004h
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SW_TILT .set 00000008h
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SW_DIAG .set 00000010h
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;SW_RES .set 00000020h
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SW_COINSRV .set 00000040h
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SW_COIN3 .set 00000080h
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SW_VOLMINUS .set 00000100h
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SW_VOLPLUS .set 00000200h
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SW_4TH .set 00000400h ;4th
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SW_3RD .set 00000800h ;3rd
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SW_2ND .set 00001000h ;2nd
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SW_1ST .set 00002000h ;1st
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SW_COIN4 .set 00004000h
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;SW_RES .set 00008000h
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SW_BRAKE .set 00010000h
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SW_RADIO .set 00020000h
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SW_LOW .set 00040000h
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SW_DEBUG .set 00080000h
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SW_VIEW .set 00100000h
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SW_VIEW0 .set 00100000h
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SW_VIEW1 .set 00200000h
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SW_VIEW2 .set 00400000h
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SW_VIEW3 .set 00800000h
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*WHEN SHIFTED DOWN 16 BITS
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SW_BRAKE_H .set 0001h
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SW_RADIO_H .set 0002h
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SW_LOW_H .set 0004h
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SW_DEBUG_H .set 0008h
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SW_VIEW_H .set 0010h
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SW_VIEW0_H .set 0010h
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SW_VIEW1_H .set 0020h
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SW_VIEW2_H .set 0040h
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SW_VIEW3_H .set 0080h
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*----------------------------------------------------------------------------
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.globl DIPRAM
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*----------------------------------------------------------------------------
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*DIP SWITCH SETTINGS
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*SW 1 (RESET)
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*SW 2
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DIP_DIAG .set 80h ;#1 DIAGNOSTIC MODE
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DIP_MOTION .set 40h ;#2 MOTION CABINET
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DIP_STANDUP .set 20h ;#3 STANDUP
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DIP_FREEZE .set 10h ;#4 FREEZE SCREEN
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; .set 8h ;#5
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DIP_COMMP .set 4h ;#6 IS LINKING PRESENT?
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DIP_LINK0 .set 2h ;#7 see comm dip settings
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DIP_LINK1 .set 1h ;#8 see comm dip settings
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*SW 3
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; .set 8000h ;#1 | \
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; .set 4000h ;#2 | \
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; .set 2000h ;#3 | COIN MODE
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; .set 1000h ;#4 |
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; .set 800h ;#5 | /
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; .set 400h ;#6 | /
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; .set 200h ;#7 (potential extra coin mode)
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DIP_COINCNTR .set 100h ;#8 FREE PLAY
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*----------------------------------------------------------------------------
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*----------------------------------------------------------------------------
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*DIP SWITCHES
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*
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CMDP_M .set 3h
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CMDP_MASTER .set 1h
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CMDP_SLAVE .set 0
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*----------------------------------------------------------------------------
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