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.FILE "MEMTEST.ASM"
*----------------------------------------------------------------------------
*MEMTEST.ASM
*
*COPYRIGHT (C) 1994 BY TV GAMES, INC.
*ALL RIGHTS RESERVED
*
*CHIP TEST ROUTINES
*
*
*MEMORY WAIT STATE ACCESS NOTES
*
*NORMAL=WAIT STATES SET TO SW=2 OR HARDWARE WHICHEVER RELEASES FIRST
*FOR COLOR RAM SET T0 SW=1 OR HARDWARE WHICHEVER RELEASES FIRST
*FOR BITMAP OR WAVERAM MODE HARDWARE ONLY
*AFTER BITMAP READ, READ 0 AFTERWARD TO RESET HDWE.
*FOR A-D SET WAIT TO SW=4 ONLY
*
.include C30.EQU
.include VUNIT.EQU
.include CMOS.EQU
.include MACS.EQU
.include SYS.EQU
.include DIAG.EQU
.include CKSUM.EQU
.include GLOBALS.EQU
.include CHECKSUM.EQU
;CHECKSUM_GEN .set 1
.text
*----------------------------------------------------------------------------
RANDI .word 5A5A5A5Ah
*----------------------------------------------------------------------------
*ROM CHIP DEFINES
* .word START_ADDR,LENGTH,MASK,SHIFT,CHKSUM_PTR
romdata
;EPROM
RTU26 .word 0E00000h,080000h,0000000FFh,0,CHKSUME00
RTU22 .word 0D80000h,080000h,0000000FFh,0,CHKSUMD80
RTU18 .word 0D00000h,080000h,0000000FFh,0,CHKSUMD00
RTU14 .word 0C80000h,080000h,0000000FFh,0,CHKSUMC80
RTU10 .word 0C00000h,080000h,0000000FFh,0,CHKSUMC00
RTU27 .word 0E00000h,080000h,00000FF00h,-8,CHKSUME01
RTU23 .word 0D80000h,080000h,00000FF00h,-8,CHKSUMD81
RTU19 .word 0D00000h,080000h,00000FF00h,-8,CHKSUMD01
RTU15 .word 0C80000h,080000h,00000FF00h,-8,CHKSUMC81
RTU11 .word 0C00000h,080000h,00000FF00h,-8,CHKSUMC01
RTU28 .word 0E00000h,080000h,000FF0000h,-16,CHKSUME02
RTU24 .word 0D80000h,080000h,000FF0000h,-16,CHKSUMD82
RTU20 .word 0D00000h,080000h,000FF0000h,-16,CHKSUMD02
RTU16 .word 0C80000h,080000h,000FF0000h,-16,CHKSUMC82
RTU12 .word 0C00000h,080000h,000FF0000h,-16,CHKSUMC02
RTU29 .word 0E00000h,080000h,0FF000000h,-24,CHKSUME03
RTU25 .word 0D80000h,080000h,0FF000000h,-24,CHKSUMD83
RTU21 .word 0D00000h,080000h,0FF000000h,-24,CHKSUMD03
RTU17 .word 0C80000h,080000h,0FF000000h,-24,CHKSUMC83
RTU13 .word 0C00000h,080000h,0FF000000h,-24,CHKSUMC03
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
*RAM CHIP DEFINES
* .word START_ADDR,LENGTH,MASK,REPETITIONS,WAIT_STATE_MODE,PRINTABLE?,UNUMBER
;WAVE RAM
RTU72 .word 0A00000h,080000h,00000000Fh,1,1000h,2
RTU69 .word 0A00000h,080000h,0000000F0h,1,1000h,2
RTU70 .word 0A00000h,080000h,000000F00h,1,1000h,2
RTU71 .word 0A00000h,080000h,00000F000h,1,1000h,2
RTU76 .word 0A00001h,080000h,00000000Fh,1,1000h,2
RTU73 .word 0A00001h,080000h,0000000F0h,1,1000h,2
RTU74 .word 0A00001h,080000h,000000F00h,1,1000h,2
RTU75 .word 0A00001h,080000h,00000F000h,1,1000h,2
;COLOR RAM
RTU85 .word 09E0000h,08000h,000FF00h,1,SOFT_WS,1
RTU87 .word 09E0000h,08000h,00000FFh,1,SOFT_WS,1
;VIDEO RAM
RTU102 .word 0900000h,020000h,0000000FFh,1,1000h,2
RTU95 .word 0900000h,020000h,00000FF00h,1,1000h,2
RTU94 .word 0900001h,020000h,0000000FFh,1,1000h,2
RTU101 .word 0900001h,020000h,00000FF00h,1,1000h,2
;FAST RAM
RTU57 .word 0400000h,020000h,00000FF00h,1,SOFT_WS,1
RTU56 .word 0400000h,020000h,0000000FFh,1,SOFT_WS,1
RTU60 .word 0400000h,020000h,0FF000000h,1,SOFT_WS,1
RTU59 .word 0400000h,020000h,000FF0000h,1,SOFT_WS,1
.text
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
*VECTOR PTR,XmYm,XM,YM,U_NUM
*
CHIPMAC .MACRO CTTP,MNX,MNY,MXX,MXY,UTP,RAMROM
.data
tt? .string ":UTP:",0
.text
.word :CTTP:,:MNX:,:MNY:,:MXX:,:MXY:,tt?,:RAMROM:
.ENDM
CHIPMC .MACRO CTTP,MNX,MNY,MXX,MXY,UTP,RAMROM
.data
tt? .string ":UTP:",0
.text
.word :CTTP:,:MNX:,:MNY:,:MNX:+:MXX:,:MNY:+:MXY:,tt?,:RAMROM:
.ENDM
ISRAM .set 0
ISROM .set 1
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
CHIPTEST_TABLEI .word CHIPTEST_TABLE
CHIPTEST_TABLE
;color ram
CHIPMC RTU85,130,250,60,16,"U85",ISRAM ;COLOR RAM
CHIPMC RTU87,130,270,60,16,"U87",ISRAM
;bitmap
CHIPMAC RTU102,300,300,350,316,"U102",ISRAM ;VIDEO RAM
CHIPMAC RTU95,300,280,350,296,"U95",ISRAM
CHIPMAC RTU94,240,280,290,296,"U94",ISRAM
CHIPMAC RTU101,240,300,290,316,"U101",ISRAM
STATIC_TABLE
CHIPMC RTU56,250,195,40,15,"U56",ISROM
CHIPMC RTU57,300,195,40,15,"U57",ISROM ;FAST RAM
CHIPMC RTU59,370,195,40,15,"U59",ISROM
CHIPMC RTU60,420,195,40,15,"U60",ISROM
TESTING_CHIPS
CHIPMAC RTU26,240,60, 290,80, "U26",ISROM ;BIG EPROM WORLD
CHIPMAC RTU22,240,85, 290,105,"U22",ISROM
CHIPMAC RTU18,240,110,290,130,"U18",ISROM
CHIPMAC RTU14,240,135,290,155,"U14",ISROM
CHIPMAC RTU10,240,160,290,180,"U10",ISROM
CHIPMAC RTU27,300,60, 350,80, "U27",ISROM ;E0
CHIPMAC RTU23,300,85, 350,105,"U23",ISROM ;D8
CHIPMAC RTU19,300,110,350,130,"U19",ISROM ;D0
CHIPMAC RTU15,300,135,350,155,"U15",ISROM ;C8
CHIPMAC RTU11,300,160,350,180,"U11",ISROM ;C0
CHIPMAC RTU28,360,60, 410,80, "U28",ISROM
CHIPMAC RTU24,360,85, 410,105,"U24",ISROM
CHIPMAC RTU20,360,110,410,130,"U20",ISROM
CHIPMAC RTU16,360,135,410,155,"U16",ISROM
CHIPMAC RTU12,360,160,410,180,"U12",ISROM
CHIPMAC RTU29,420,60, 470,80, "U29",ISROM
CHIPMAC RTU25,420,85, 470,105,"U25",ISROM
CHIPMAC RTU21,420,110,470,130,"U21",ISROM
CHIPMAC RTU17,420,135,470,155,"U17",ISROM
CHIPMAC RTU13,420,160,470,180,"U13",ISROM
CHIPMC RTU69,360,220,40,14,"U69",ISRAM
CHIPMC RTU70,360,240,40,14,"U70",ISRAM
CHIPMC RTU71,360,260,40,14,"U71",ISRAM
CHIPMC RTU72,360,280,40,14,"U72",ISRAM ;WAVE RAM
CHIPMC RTU73,410,220,40,14,"U73",ISRAM
CHIPMC RTU74,410,240,40,14,"U74",ISRAM
CHIPMC RTU75,410,260,40,14,"U75",ISRAM
CHIPMC RTU76,410,280,40,14,"U76",ISRAM ;WAVE RAM
.word 0
RTU31 ;nothing...
CMOS_CHIP
CHIPMC RTU31,130,120,40,18,"U31",ISROM ;CMOS CHIP
*----------------------------------------------------------------------------
*STRUCT CHIP_TEST_TABLE
CTT_TESTTAB .set 0
CTT_MINX .set 1
CTT_MINY .set 2
CTT_MAXX .set 3
CTT_MAXY .set 4
CTT_U .set 5
CTT_RAMROM .set 6
CTT_SIZE .set 7
*ENDSTRUCT
*----------------------------------------------------------------------------
*TEST_CHIPS Controller Routine
*
*
* 1. THE STACK IS ONCHIP, THEREFORE WE CAN ASSUME
* THAT IT WORKS, THEREFORE WE MAY USE CALLs
* TO SUBROUTINES.
* 2. DESIGNED TO BE RUN OUT OF ROM
* 3. INTERRUPTS SHOULD BE TURNED OFF
* 4. AFTERWARDS RAM SHOULD BE CLEARED
* 5. ON CHIP RAM IS NOT TESTED (OBVIOUSLY)
* 6. ROUTINE IS CALLED (SEE #1)
* 7. SPACE MUST BE RESERVED FOR THE FOLLOWING TWO
* ROUTINES ON ONCHIP RAM:
* RAMTEST (this file)
* _pixel (FONT1A.ASM)
* BECAUSE THESE ROUTINES CHANGE WAIT STATES (WHICH
* CAN NOT HAPPEN DURING PROGRAM FETCH FROM SLOW
* ROM (see #2)).
*
.globl TEST_STATIC_CHIPS
TEST_STATIC_CHIPS:
DINT
SETDP
CALL COPY_RAMTEST
LDL BASICS_RAM,AR5
LDI 3,AR6
LDL STATIC_TABLE,AR4
TSTBL1A
LDI *+AR4(CTT_TESTTAB),AR0
LDI *AR0++,AR2
LDI *AR0++,R2
LDI *AR0++,R3
LDI *AR0++,RC
LDI *AR0++,RS
LDI *AR0++,BK
.globl FEED_WATCHDOG_HARD
CALL FEED_WATCHDOG_HARD
PUSH AR0
PUSH AR6
PUSH AR5
PUSH AR4
CALL RAMTEST
POP AR4
POP AR5
POP AR6
POP AR0
STI R0,*AR5++ ;SAVE RESULTS
CMPI 1,R0
BEQ IS_STATIC_ERROR
LDI *++AR4(CTT_SIZE),R0
DBU AR6,TSTBL1A
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
GET_AR4_DIGITS:
LDI *+AR4(CTT_U),AR0
LDI *AR0,AR0
LDI AR0,R1
RS 8,R1
AND 0FFh,R1
SUBI '0',R1
LDI AR0,R2
RS 16,R2
AND 0FFh,R2
CMPI 0,R2
BEQ R1R2ZER
SUBI '0',R2
LDI AR0,R3
RS 24,R3
AND 0FFh,R3
CMPI 0,R3
BEQ R3ZERO
SUBI '0',R3
BU NZERO
R1R2ZER CLRI R2
R3ZERO CLRI R3
NZERO
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
BLINK_AND_CONTINUE:
PUSH RS
PUSH RE
PUSH RC
PUSH AR0
PUSH R1
PUSH R2
PUSH R3
CALL GET_AR4_DIGITS
CALL BLINK_DIGITS
POP R3
POP R2
POP R1
POP AR0
POP RC
POP RE
POP RS
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
IS_STATIC_ERROR:
CALL GET_AR4_DIGITS
ELOOP
CALL BLINK_DIGITS
BU ELOOP
*----------------------------------------------------------------------------
*
*THIS ROUTINE TAKES OVER THE CPU, AND RETURNS
*
*PARAMETERS
* R1 DIGIT 1
* R2 DIGIT 2
* R3 DIGIT 3
*
*
LLED_ON:
LDI @SYSCNTL,R0 ;if the system hangs and the LED
ANDN LED_OFF,R0 ;is on we were in this routine
STI R0,@SYSCNTL ;when it happened
LDP @SYSCNTLR
STI R0,@SYSCNTLR
SETDP
RETS
LLED_OFF:
LDI @SYSCNTL,R0
OR LED_OFF,R0
STI R0,@SYSCNTL
LDP @SYSCNTLR
STI R0,@SYSCNTLR
SETDP
RETS
BLINK_DIGITS:
PUSH R0
PUSH R1
PUSH R2
PUSH R3
PUSH AR4
LDI R1,AR4 ;#NUMBER OF ITERATIONS
DEC AR4
CMPI 0,AR4
BLT BDL1X
BDL1
CALL LLED_ON
LDIL 8000000,RC
RPTS RC
NOP
CALL LLED_OFF
LDIL 8000000,RC
RPTS RC
NOP
DBU AR4,BDL1
BDL1X
LDIL 35000000,RC
RPTS RC
NOP
LDI R2,AR4 ;#NUMBER OF ITERATIONS
DEC AR4
CMPI 0,AR4
BLT BDL2X
BDL2
CALL LLED_ON
LDIL 8000000,RC
RPTS RC
NOP
CALL LLED_OFF
LDIL 8000000,RC
RPTS RC
NOP
DBU AR4,BDL2
BDL2X
LDIL 35000000,RC
RPTS RC
NOP
LDI R3,AR4 ;#NUMBER OF ITERATIONS
DEC AR4
CMPI 0,AR4
BLT BDL3X
BDL3 CALL LLED_ON
LDIL 8000000,RC
RPTS RC
NOP
CALL LLED_OFF
LDIL 8000000,RC
RPTS RC
NOP
DBU AR4,BDL3
BDL3X
LDIL 35000000,RC
RPTS RC
NOP
LDIL 35000000,RC
RPTS RC
NOP
POP AR4
POP R3
POP R2
POP R1
POP R0
RETS
*----------------------------------------------------------------------------
TEST_CHIPS:
PUSH DP
LDP @9E0000h
CLRI R0 ;set background to 0
STI R0,@9E0000h
POP DP
CALL SETPAGE0
LDIL SCREEN0,R0 ;set active screen to 1 (writeable)
STI R0,@ACTIVE_SCREEN
DINT
CALL COPY_RAMTEST
CALL TEST_BASICS
LDI COL_VDGREY,RC
TEXTITT "CPU BOARD TEST",50,40
;
;NOW CHECK AND PLOT ACCORDINGLY
;
LDL TESTING_CHIPS,AR4
TESTLP1
LDI *+AR4(CTT_RAMROM),R0
BZ CHECK_AS_RAM ;(W/ SCRAMBLE)
LDI *+AR4(CTT_TESTTAB),AR0
LDI *AR0++,AR2 ;ADDR
LDI *AR0++,RC ;LENGTH
LDI *AR0++,R2 ;MASK
LDI *AR0++,R3 ;SHIFT
CALL GENERATE_CHECKSUM
LDI *AR0,AR0
LDI *AR0,R1
CMPI R1,R0
LDIEQ COL_GREEN,RS
LDINE COL_RED,RS
; CMPI COL_RED,RS
; CALLEQ BLINK_AND_CONTINUE
;CHECKSUM PART
BU DN_CHK
CHECK_AS_RAM
LDI *+AR4(CTT_TESTTAB),AR0
CMPI -1,AR0
BEQ TEST_CHIPSX
LDI *AR0++,AR2
LDI *AR0++,R2
LDI *AR0++,R3
LDI *AR0++,RC
LDI *AR0++,RS
LDI *AR0++,BK
PUSH AR0
PUSH AR4
CALL RAMTEST
POP AR4
POP AR0
LDI R0,R0
LDIZ COL_GREEN,RS
; LDIZ COL_GREY,RS
LDINZ COL_RED,RS
; CMPI COL_RED,RS
; CALLEQ BLINK_AND_CONTINUE
DN_CHK
LDI *+AR4(CTT_MINX),AR2
INC AR2
LDI *+AR4(CTT_MINY),R2
INC R2
LDI *+AR4(CTT_MAXX),R3
DEC R3
LDI *+AR4(CTT_MAXY),RC
DEC RC
CALL _fill
LDI *+AR4(CTT_U),AR2
LDI *+AR4(CTT_MAXX),R2
LDI *+AR4(CTT_MAXY),R3
SUBI *+AR4(CTT_MINX),R2
SUBI *+AR4(CTT_MINY),R3
RS 1,R2
RS 1,R3
ADDI *+AR4(CTT_MINX),R2
ADDI *+AR4(CTT_MINY),R3
SUBI 15,R2
SUBI 4,R3
LDI COL_BLACK,RC
CALL _outtextxyc
LDI *++AR4(CTT_SIZE),R0
BNZ TESTLP1
TEST_CHIPSX
CALL CMOS_CHIP_TEST
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
PLOT_OUTLINE_OF_CHIPS:
LDI @CHIPTEST_TABLEI,AR4
POOCL
LDI *+AR4(CTT_MINX),AR2
LDI *+AR4(CTT_MINY),R2
LDI *+AR4(CTT_MAXX),R3
LDI *+AR4(CTT_MAXY),RC
LDI COL_WHITE,RS
PUSH DP
CALL _rectangle
POP DP
LDI *+AR4(CTT_U),AR2
LDI *+AR4(CTT_MAXX),R2
LDI *+AR4(CTT_MAXY),R3
SUBI *+AR4(CTT_MINX),R2
SUBI *+AR4(CTT_MINY),R3
RS 1,R2
RS 1,R3
ADDI *+AR4(CTT_MINX),R2
ADDI *+AR4(CTT_MINY),R3
SUBI 15,R2
SUBI 4,R3
LDI COL_DGREY,RC
CALL _outtextxyc
LDI *++AR4(CTT_SIZE),R0
BNZ POOCL
CALL CMOS_CHIP_DISPLAY
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
CMOS_CHIP_DISPLAY:
LDL CMOS_CHIP,AR4
LDI *+AR4(CTT_MINX),AR2
LDI *+AR4(CTT_MINY),R2
LDI *+AR4(CTT_MAXX),R3
LDI *+AR4(CTT_MAXY),RC
LDI COL_WHITE,RS
PUSH DP
CALL _rectangle
POP DP
LDI *+AR4(CTT_U),AR2
LDI *+AR4(CTT_MAXX),R2
LDI *+AR4(CTT_MAXY),R3
SUBI *+AR4(CTT_MINX),R2
SUBI *+AR4(CTT_MINY),R3
RS 1,R2
RS 1,R3
ADDI *+AR4(CTT_MINX),R2
ADDI *+AR4(CTT_MINY),R3
SUBI 15,R2
SUBI 4,R3
LDI COL_DGREY,RC
CALL _outtextxyc
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
CMOS_CHIP_TEST:
PUSH AR4
PUSH R0
PUSH R1
PUSH R2
PUSH R3
LDL CMOS_CHIP,AR4
LDIL 5A5A5A5Ah,R3
LDP @CPU_WS
LDI 88h,R1
STI R1,@CPU_WS
SETDP
CMOS_WP_OFF
NOP ;DELAY FOR TIMING...
LDI 5,AR5
KKLL1 LDI R3,R2
AND 0FFh,R2
LS 24,R2
LDI AUD_CHIPTEST_DEDICATED,AR2
LS 2,AR2
ADDI @CMOSI,AR2
STI R2,*AR2
RS 24,R2
LDL 0C00000h,AR0 ;DUMMY READ
LDI *AR0,R0
LDI *AR2,R0
RS 24,R0
CMPI R2,R0
BNE CM_ISERROR
LDI R3,R1
LSH 1,R3
XOR R3,R1
BNN RND2
OR 1,R3
RND2 MPYI 794Fh,R3
DBU AR5,KKLL1
CMOS_WP_ON
;NO ERROR
LDI COL_GREEN,RS
BU KKJJ
CM_ISERROR
CMOS_WP_ON
LDI COL_RED,RS
KKJJ
; CMPI COL_RED,RS
; CALLEQ BLINK_AND_CONTINUE
LDP @CPU_WS
LDI 1048h,R0
STI R0,@CPU_WS
SETDP
LDI *+AR4(CTT_MINX),AR2
INC AR2
LDI *+AR4(CTT_MINY),R2
INC R2
LDI *+AR4(CTT_MAXX),R3
DEC R3
LDI *+AR4(CTT_MAXY),RC
DEC RC
CALL _fill
LDI *+AR4(CTT_U),AR2
LDI *+AR4(CTT_MAXX),R2
LDI *+AR4(CTT_MAXY),R3
SUBI *+AR4(CTT_MINX),R2
SUBI *+AR4(CTT_MINY),R3
RS 1,R2
RS 1,R3
ADDI *+AR4(CTT_MINX),R2
ADDI *+AR4(CTT_MINY),R3
SUBI 15,R2
SUBI 4,R3
LDI COL_BLACK,RC
CALL _outtextxyc
POP R3
POP R2
POP R1
POP R0
POP AR4
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
*FOR THE DISPLAY TO WORK WE MUST HAVE OPERATING PROPERLY:
* VIDEO RAM (8 CHIPS)
* COLOR RAM (2 CHIPS)
*SO, WE TEST THESE (NOT PLOTTING TO THE SCREEN), AND SAVE THE RESULTS,
*THEN WE BEGIN PLOTTING THE SCREEN, INITIALIZATING THESE SPACES WITH THE
*RESULTS.
*
*
fbss BASICS_RAM,10
TEST_BASICS:
LDL BASICS_RAM,AR5
LDI 5,AR6
LDL CHIPTEST_TABLE,AR4
TSTBL1
LDI *+AR4(CTT_TESTTAB),AR0
LDI *AR0++,AR2
LDI *AR0++,R2
LDI *AR0++,R3
LDI *AR0++,RC
LDI *AR0++,RS
LDI *AR0++,BK
PUSH AR0
PUSH AR6
PUSH AR5
PUSH AR4
CALL RAMTEST
POP AR4
POP AR5
POP AR6
POP AR0
STI R0,*AR5++ ;SAVE RESULTS
CMPI 0,R0
CALLNZ BLINK_AND_CONTINUE
LDI *++AR4(CTT_SIZE),R0
DBU AR6,TSTBL1
.globl HARD_LOAD_DIAGPAL
CALL HARD_LOAD_DIAGPAL
CLRI R0
STI R0,@COLORAM
CALL CLRSCRN ;we are NOT page flipping
PUSH DP
LINE 20,50,490,50,COL_WHITE
LINE 20,50,20,360,COL_WHITE
LINE 490,50,490,360,COL_WHITE
LINE 20,360,80,360,COL_WHITE
LINE 80,360,80,340,COL_WHITE
LINE 80,340,100,340,COL_WHITE
LINE 100,340,100,360,COL_WHITE
LINE 100,360,200,360,COL_WHITE
LINE 200,360,200,340,COL_WHITE
LINE 200,340,220,340,COL_WHITE
LINE 220,340,220,360,COL_WHITE
LINE 220,360,490,360,COL_WHITE
POP DP
CALL PLOT_OUTLINE_OF_CHIPS
romdata
MEMTST1 .string "CRUISN USA (TM)",0
.text
LDI COL_VDGREY,RC
TEXTIT MEMTST1,50,20
TEXTIT DATE_STAMP,50,30
TEXTIT VERSION_STAMP,270,30
LDL BASICS_RAM,AR5
LDI 9,AR6
LDL CHIPTEST_TABLE,AR4
TSTBL2
LDI *AR5++,R0 ;SAVE RESULTS
LDIZ COL_GREEN,RS
LDINZ COL_RED,RS
LDI *+AR4(CTT_MINX),AR2
INC AR2
LDI *+AR4(CTT_MINY),R2
INC R2
LDI *+AR4(CTT_MAXX),R3
DEC R3
LDI *+AR4(CTT_MAXY),RC
DEC RC
CALL _fill
LDI *+AR4(CTT_U),AR2
LDI *+AR4(CTT_MAXX),R2
LDI *+AR4(CTT_MAXY),R3
SUBI *+AR4(CTT_MINX),R2
SUBI *+AR4(CTT_MINY),R3
RS 1,R2
RS 1,R3
ADDI *+AR4(CTT_MINX),R2
ADDI *+AR4(CTT_MINY),R3
SUBI 15,R2
SUBI 4,R3
LDI COL_BLACK,RC
CALL _outtextxyc
LDI *++AR4(CTT_SIZE),R0
DBU AR6,TSTBL2
;Static *MUST* be working to get this far,
;so mark them ALL as cool
;
LDI 3,AR6
LDL STATIC_TABLE,AR4
TSTBL2C
LDI COL_GREEN,RS
LDI *+AR4(CTT_MINX),AR2
INC AR2
LDI *+AR4(CTT_MINY),R2
INC R2
LDI *+AR4(CTT_MAXX),R3
DEC R3
LDI *+AR4(CTT_MAXY),RC
DEC RC
CALL _fill
LDI *+AR4(CTT_U),AR2
LDI *+AR4(CTT_MAXX),R2
LDI *+AR4(CTT_MAXY),R3
SUBI *+AR4(CTT_MINX),R2
SUBI *+AR4(CTT_MINY),R3
RS 1,R2
RS 1,R3
ADDI *+AR4(CTT_MINX),R2
ADDI *+AR4(CTT_MINY),R3
SUBI 15,R2
SUBI 4,R3
LDI COL_BLACK,RC
CALL _outtextxyc
LDI *++AR4(CTT_SIZE),R0
DBU AR6,TSTBL2C
CALL CMOS_CHIP_TEST
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
*TEST RAM AREA
*CALLING PARAMETERS
*
*PARAMETERS
* AR2 START ADDR
* R2 LENGTH WORDS
* R3 MASK (FOR BYTE WIDE CHIPS)
* RC # OF PASSES
* RS WAIT STATE CODE
* BK INCREMENT (USUALLY 1)
*
*RETURNS
* R0 1 ON ERROR
* R0 0 ON NO ERROR
*
*CLOBBERS
* DP,RS,RE,RC
* R0,R1,R2,R3,R4,R5
* AR0,AR1,AR2,AR3
*USES
* AR6 WATCHDOG FEEDER
*
*
RAMTEST: ;THIS IS CALLED DURING RUNTIME
LDL BLOWLIST,R0
BU R0
;THIS IS THE ACTUAL ROUTINE, BUT IT MUST
;BE PLACED IN ON-CHIP MEMORY
;
RAMTEST_REAL:
PUSH DP
PUSH R6
PUSH AR6
LCALL FEED_WATCHDOG_HARD
LDP @CPU_WS ;set hardware wait states
LDI @CPU_WS,R0
PUSH R0
STI RS,@CPU_WS
LDI 0,AR3 ;DUMMY READ ADDRESS
LDI *AR3,R5 ;DUMMY READ
LDP @RANDI
LDI @RANDI,R4 ;SETUP R4=RANDOM # REGISTER
LDI RC,AR0 ;NUMBER OF PASSES
DEC AR0
DEC R2 ;LENGTH OF CHECK
LDI R2,AR4
RAMTST0
LDI AR2,AR1 ;GET ADDRESS
LDI R4,R0 ;GET RANDOM # STARTING POINT
*WRITE RANDOM NUMBERS TO RAM
RAMTST1
LDI R0,R1
LSH 1,R0
LDI 0,R6
XOR R0,R1
LDIN 2,R6 ; BNN RAMTST2
OR R6,R0 ; OR 2,R0
;RAMTST2
DBUD AR4,RAMTST1
STI R0,*AR1
ADDI BK,AR1
LKKK LDI *AR3,R5 ;DUMMY READ
*READ RANDOM NUMBERS FROM RAM
LDI AR2,AR1 ;GET ADDRESS
LDI R4,R0 ;GET RANDOM # STARTING POINT
LDI R0,R1
LSH 1,R0
CLRI R6
CLRI R7
LDI R2,AR4 ;LENGTH
XOR R0,R1
LDIN 2,R6 ; BNN RAMTST4
RAMTST3
OR R6,R0 ; OR 2,R0
;RAMTST4
INC R7
LDI *AR1,R1
ADDI BK,AR1
LDI *AR3,R5 ;DUMMY READ
AND R3,R1
LDI R0,R4
AND R3,R0
CMPI R1,R0
BNE RAMERR
LDI R4,R0
LDI R0,R1 ;mirrored from above
LSH 1,R0
;---->BNE RAMERR
DBUD AR4,RAMTST3
JJJH CLRI R6
XOR R0,R1
LDIN 2,R6 ; BNN RAMTST4
;----> DBUD AR4,RAMTST3
RAMRPT
DBU AR0,RAMTST0
CLRI R0 ;IS GOOD RAM
ENDING
POP R1 ;FIND WAIT STATES
LDP @CPU_WS ;set original wait states
STI R1,@CPU_WS
POP AR6
POP R6
POP DP
RETS
RAMERR:
LDI 1,R0 ;IS BAD RAM
BU ENDING
RAMTEST_END:
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
COPY_RAMTEST:
LDL RAMTEST_END,AR0
LDL RAMTEST_REAL,AR1
SUBI AR1,AR0 ;GET LENGTH
DEC AR0
LDL BLOWLIST,AR2
LDI AR0,RC
RPTB BBCP
LDI *AR1++,R0
BBCP STI R0,*AR2++
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
*GENERATE_CHECKSUM
*
*GENERATES A 16 BIT CHECKSUM
*
*
*PARAMETERS
* AR2 START ADDR
* RC LENGTH WORDS
* R2 MASK
* R3 SHIFT
*
*RETURNS
* R0 PART CHECKSUM
*
GENERATE_CHECKSUM:
PUSH R1
PUSH RC
PUSH AR2
LCALL FEED_WATCHDOG
CLRI R0
DEC RC
RPTB CHKSUMG
LDI *AR2++,R1
AND R2,R1
LSH R3,R1
CHKSUMG ADDI R1,R0
LS 16,R0
RS 16,R0
POP AR2
POP RC
POP R1
RETS
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
*ROM CHIP CHECKSUMS
*
.if CHECKSUM_GEN
CHKSUMC00 .word -1
CHKSUMC80 .word -1
CHKSUMD00 .word -1
CHKSUMD80 .word -1
CHKSUME00 .word -1
CHKSUMC01 .word -1
CHKSUMC81 .word -1
CHKSUMD01 .word -1
CHKSUMD81 .word -1
CHKSUME01 .word -1
CHKSUMC02 .word -1
CHKSUMC82 .word -1
CHKSUMD02 .word -1
CHKSUMD82 .word -1
CHKSUME02 .word -1
CHKSUMC03 .word -1
CHKSUMC83 .word -1
CHKSUMD03 .word -1
CHKSUMD83 .word -1
CHKSUME03 .word -1
CCHKSUMC00 .word 0
CCHKSUMC80 .word 0
CCHKSUMD00 .word 0
CCHKSUMD80 .word 0
CCHKSUME00 .word 0
CCHKSUMC01 .word 0
CCHKSUMC81 .word 0
CCHKSUMD01 .word 0
CCHKSUMD81 .word 0
CCHKSUME01 .word 0
CCHKSUMC02 .word 0
CCHKSUMC82 .word 0
CCHKSUMD02 .word 0
CCHKSUMD82 .word 0
CCHKSUME02 .word 0
CCHKSUMC03 .word 0
CCHKSUMC83 .word 0
CCHKSUMD03 .word 0
CCHKSUMD83 .word 0
CCHKSUME03 .word 0
.else
CHKSUMC00 .word CHECKSUM_C00
CHKSUMC80 .word CHECKSUM_C80
CHKSUMD00 .word CHECKSUM_D00
CHKSUMD80 .word CHECKSUM_D80
CHKSUME00 .word CHECKSUM_E00
CHKSUMC01 .word CHECKSUM_C01
CHKSUMC81 .word CHECKSUM_C81
CHKSUMD01 .word CHECKSUM_D01
CHKSUMD81 .word CHECKSUM_D81
CHKSUME01 .word CHECKSUM_E01
CHKSUMC02 .word CHECKSUM_C02
CHKSUMC82 .word CHECKSUM_C82
CHKSUMD02 .word CHECKSUM_D02
CHKSUMD82 .word CHECKSUM_D82
CHKSUME02 .word CHECKSUM_E02
CHKSUMC03 .word CHECKSUM_C03
CHKSUMC83 .word CHECKSUM_C83
CHKSUMD03 .word CHECKSUM_D03
CHKSUMD83 .word CHECKSUM_D83
CHKSUME03 .word CHECKSUM_E03
CCHKSUMC00 .word ~CHECKSUM_C00
CCHKSUMC80 .word ~CHECKSUM_C80
CCHKSUMD00 .word ~CHECKSUM_D00
CCHKSUMD80 .word ~CHECKSUM_D80
CCHKSUME00 .word ~CHECKSUM_E00
CCHKSUMC01 .word ~CHECKSUM_C01
CCHKSUMC81 .word ~CHECKSUM_C81
CCHKSUMD01 .word ~CHECKSUM_D01
CCHKSUMD81 .word ~CHECKSUM_D81
CCHKSUME01 .word ~CHECKSUM_E01
CCHKSUMC02 .word ~CHECKSUM_C02
CCHKSUMC82 .word ~CHECKSUM_C82
CCHKSUMD02 .word ~CHECKSUM_D02
CCHKSUMD82 .word ~CHECKSUM_D82
CCHKSUME02 .word ~CHECKSUM_E02
CCHKSUMC03 .word ~CHECKSUM_C03
CCHKSUMC83 .word ~CHECKSUM_C83
CCHKSUMD03 .word ~CHECKSUM_D03
CCHKSUMD83 .word ~CHECKSUM_D83
CCHKSUME03 .word ~CHECKSUM_E03
.endif
*----------------------------------------------------------------------------
.END
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