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Merge pull request #1705 from josepho0918/dev

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Add support for IAR C/C++ Compiler for Arm
This commit is contained in:
Yann Collet 2019-08-05 15:57:28 +02:00 committed by GitHub
commit 61936ba42a
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 18 additions and 6 deletions
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4
lib/common/bitstream.h
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@ -57,6 +57,8 @@ extern "C" {
=========================================*/ =========================================*/
#if defined(__BMI__) && defined(__GNUC__) #if defined(__BMI__) && defined(__GNUC__)
# include <immintrin.h> /* support for bextr (experimental) */ # include <immintrin.h> /* support for bextr (experimental) */
#elif defined(__ICCARM__)
# include <intrinsics.h>
#endif #endif
#define STREAM_ACCUMULATOR_MIN_32 25 #define STREAM_ACCUMULATOR_MIN_32 25
@ -163,6 +165,8 @@ MEM_STATIC unsigned BIT_highbit32 (U32 val)
return (unsigned) r; return (unsigned) r;
# elif defined(__GNUC__) && (__GNUC__ >= 3) /* Use GCC Intrinsic */ # elif defined(__GNUC__) && (__GNUC__ >= 3) /* Use GCC Intrinsic */
return 31 - __builtin_clz (val); return 31 - __builtin_clz (val);
# elif defined(__ICCARM__) /* IAR Intrinsic */
return 31 - __CLZ(val);
# else /* Software version */ # else /* Software version */
static const unsigned DeBruijnClz[32] = { 0, 9, 1, 10, 13, 21, 2, 29, static const unsigned DeBruijnClz[32] = { 0, 9, 1, 10, 13, 21, 2, 29,
11, 14, 16, 18, 22, 25, 3, 30, 11, 14, 16, 18, 22, 25, 3, 30,

6
lib/common/compiler.h
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@ -23,7 +23,7 @@
# define INLINE_KEYWORD # define INLINE_KEYWORD
#endif #endif
#if defined(__GNUC__) #if defined(__GNUC__) || defined(__ICCARM__)
# define FORCE_INLINE_ATTR __attribute__((always_inline)) # define FORCE_INLINE_ATTR __attribute__((always_inline))
#elif defined(_MSC_VER) #elif defined(_MSC_VER)
# define FORCE_INLINE_ATTR __forceinline # define FORCE_INLINE_ATTR __forceinline
@ -65,7 +65,7 @@
#ifdef _MSC_VER #ifdef _MSC_VER
# define FORCE_NOINLINE static __declspec(noinline) # define FORCE_NOINLINE static __declspec(noinline)
#else #else
# ifdef __GNUC__ # if defined(__GNUC__) || defined(__ICCARM__)
# define FORCE_NOINLINE static __attribute__((__noinline__)) # define FORCE_NOINLINE static __attribute__((__noinline__))
# else # else
# define FORCE_NOINLINE static # define FORCE_NOINLINE static
@ -76,7 +76,7 @@
#ifndef __has_attribute #ifndef __has_attribute
#define __has_attribute(x) 0 /* Compatibility with non-clang compilers. */ #define __has_attribute(x) 0 /* Compatibility with non-clang compilers. */
#endif #endif
#if defined(__GNUC__) #if defined(__GNUC__) || defined(__ICCARM__)
# define TARGET_ATTRIBUTE(target) __attribute__((__target__(target))) # define TARGET_ATTRIBUTE(target) __attribute__((__target__(target)))
#else #else
# define TARGET_ATTRIBUTE(target) # define TARGET_ATTRIBUTE(target)

2
lib/common/mem.h
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@ -102,7 +102,7 @@ MEM_STATIC void MEM_check(void) { MEM_STATIC_ASSERT((sizeof(size_t)==4) || (size
#ifndef MEM_FORCE_MEMORY_ACCESS /* can be defined externally, on command line for example */ #ifndef MEM_FORCE_MEMORY_ACCESS /* can be defined externally, on command line for example */
# if defined(__GNUC__) && ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) ) # if defined(__GNUC__) && ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) )
# define MEM_FORCE_MEMORY_ACCESS 2 # define MEM_FORCE_MEMORY_ACCESS 2
# elif defined(__INTEL_COMPILER) || defined(__GNUC__) # elif defined(__INTEL_COMPILER) || defined(__GNUC__) || defined(__ICCARM__)
# define MEM_FORCE_MEMORY_ACCESS 1 # define MEM_FORCE_MEMORY_ACCESS 1
# endif # endif
#endif #endif

10
lib/common/xxhash.c
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@ -53,7 +53,8 @@
# if defined(__GNUC__) && ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) ) # if defined(__GNUC__) && ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) )
# define XXH_FORCE_MEMORY_ACCESS 2 # define XXH_FORCE_MEMORY_ACCESS 2
# elif (defined(__INTEL_COMPILER) && !defined(WIN32)) || \ # elif (defined(__INTEL_COMPILER) && !defined(WIN32)) || \
(defined(__GNUC__) && ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) )) (defined(__GNUC__) && ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) )) || \
defined(__ICCARM__)
# define XXH_FORCE_MEMORY_ACCESS 1 # define XXH_FORCE_MEMORY_ACCESS 1
# endif # endif
#endif #endif
@ -120,7 +121,7 @@ static void* XXH_memcpy(void* dest, const void* src, size_t size) { return memcp
# define INLINE_KEYWORD # define INLINE_KEYWORD
#endif #endif
#if defined(__GNUC__) #if defined(__GNUC__) || defined(__ICCARM__)
# define FORCE_INLINE_ATTR __attribute__((always_inline)) # define FORCE_INLINE_ATTR __attribute__((always_inline))
#elif defined(_MSC_VER) #elif defined(_MSC_VER)
# define FORCE_INLINE_ATTR __forceinline # define FORCE_INLINE_ATTR __forceinline
@ -206,7 +207,12 @@ static U64 XXH_read64(const void* memPtr)
# define XXH_rotl32(x,r) _rotl(x,r) # define XXH_rotl32(x,r) _rotl(x,r)
# define XXH_rotl64(x,r) _rotl64(x,r) # define XXH_rotl64(x,r) _rotl64(x,r)
#else #else
#if defined(__ICCARM__)
# include <intrinsics.h>
# define XXH_rotl32(x,r) __ROR(x,(32 - r))
#else
# define XXH_rotl32(x,r) ((x << r) | (x >> (32 - r))) # define XXH_rotl32(x,r) ((x << r) | (x >> (32 - r)))
#endif
# define XXH_rotl64(x,r) ((x << r) | (x >> (64 - r))) # define XXH_rotl64(x,r) ((x << r) | (x >> (64 - r)))
#endif #endif

2
lib/common/zstd_internal.h
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@ -324,6 +324,8 @@ MEM_STATIC U32 ZSTD_highbit32(U32 val) /* compress, dictBuilder, decodeCorpus
return (unsigned)r; return (unsigned)r;
# elif defined(__GNUC__) && (__GNUC__ >= 3) /* GCC Intrinsic */ # elif defined(__GNUC__) && (__GNUC__ >= 3) /* GCC Intrinsic */
return 31 - __builtin_clz(val); return 31 - __builtin_clz(val);
# elif defined(__ICCARM__) /* IAR Intrinsic */
return 31 - __CLZ(val);
# else /* Software version */ # else /* Software version */
static const U32 DeBruijnClz[32] = { 0, 9, 1, 10, 13, 21, 2, 29, 11, 14, 16, 18, 22, 25, 3, 30, 8, 12, 20, 28, 15, 17, 24, 7, 19, 27, 23, 6, 26, 5, 4, 31 }; static const U32 DeBruijnClz[32] = { 0, 9, 1, 10, 13, 21, 2, 29, 11, 14, 16, 18, 22, 25, 3, 30, 8, 12, 20, 28, 15, 17, 24, 7, 19, 27, 23, 6, 26, 5, 4, 31 };
U32 v = val; U32 v = val;