Merge pull request #1705 from josepho0918/dev
Add support for IAR C/C++ Compiler for Arm
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61936ba42a
@ -57,6 +57,8 @@ extern "C" {
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=========================================*/
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#if defined(__BMI__) && defined(__GNUC__)
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# include <immintrin.h> /* support for bextr (experimental) */
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#elif defined(__ICCARM__)
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# include <intrinsics.h>
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#endif
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#define STREAM_ACCUMULATOR_MIN_32 25
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@ -163,6 +165,8 @@ MEM_STATIC unsigned BIT_highbit32 (U32 val)
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return (unsigned) r;
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# elif defined(__GNUC__) && (__GNUC__ >= 3) /* Use GCC Intrinsic */
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return 31 - __builtin_clz (val);
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# elif defined(__ICCARM__) /* IAR Intrinsic */
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return 31 - __CLZ(val);
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# else /* Software version */
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static const unsigned DeBruijnClz[32] = { 0, 9, 1, 10, 13, 21, 2, 29,
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11, 14, 16, 18, 22, 25, 3, 30,
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@ -23,7 +23,7 @@
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# define INLINE_KEYWORD
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#endif
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#if defined(__GNUC__)
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#if defined(__GNUC__) || defined(__ICCARM__)
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# define FORCE_INLINE_ATTR __attribute__((always_inline))
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#elif defined(_MSC_VER)
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# define FORCE_INLINE_ATTR __forceinline
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@ -65,7 +65,7 @@
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#ifdef _MSC_VER
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# define FORCE_NOINLINE static __declspec(noinline)
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#else
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# ifdef __GNUC__
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# if defined(__GNUC__) || defined(__ICCARM__)
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# define FORCE_NOINLINE static __attribute__((__noinline__))
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# else
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# define FORCE_NOINLINE static
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@ -76,7 +76,7 @@
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#ifndef __has_attribute
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#define __has_attribute(x) 0 /* Compatibility with non-clang compilers. */
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#endif
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#if defined(__GNUC__)
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#if defined(__GNUC__) || defined(__ICCARM__)
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# define TARGET_ATTRIBUTE(target) __attribute__((__target__(target)))
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#else
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# define TARGET_ATTRIBUTE(target)
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@ -102,7 +102,7 @@ MEM_STATIC void MEM_check(void) { MEM_STATIC_ASSERT((sizeof(size_t)==4) || (size
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#ifndef MEM_FORCE_MEMORY_ACCESS /* can be defined externally, on command line for example */
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# if defined(__GNUC__) && ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) )
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# define MEM_FORCE_MEMORY_ACCESS 2
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# elif defined(__INTEL_COMPILER) || defined(__GNUC__)
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# elif defined(__INTEL_COMPILER) || defined(__GNUC__) || defined(__ICCARM__)
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# define MEM_FORCE_MEMORY_ACCESS 1
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# endif
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#endif
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@ -53,7 +53,8 @@
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# if defined(__GNUC__) && ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) )
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# define XXH_FORCE_MEMORY_ACCESS 2
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# elif (defined(__INTEL_COMPILER) && !defined(WIN32)) || \
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(defined(__GNUC__) && ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) ))
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(defined(__GNUC__) && ( defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) )) || \
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defined(__ICCARM__)
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# define XXH_FORCE_MEMORY_ACCESS 1
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# endif
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#endif
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@ -120,7 +121,7 @@ static void* XXH_memcpy(void* dest, const void* src, size_t size) { return memcp
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# define INLINE_KEYWORD
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#endif
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#if defined(__GNUC__)
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#if defined(__GNUC__) || defined(__ICCARM__)
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# define FORCE_INLINE_ATTR __attribute__((always_inline))
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#elif defined(_MSC_VER)
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# define FORCE_INLINE_ATTR __forceinline
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@ -206,7 +207,12 @@ static U64 XXH_read64(const void* memPtr)
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# define XXH_rotl32(x,r) _rotl(x,r)
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# define XXH_rotl64(x,r) _rotl64(x,r)
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#else
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#if defined(__ICCARM__)
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# include <intrinsics.h>
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# define XXH_rotl32(x,r) __ROR(x,(32 - r))
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#else
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# define XXH_rotl32(x,r) ((x << r) | (x >> (32 - r)))
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#endif
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# define XXH_rotl64(x,r) ((x << r) | (x >> (64 - r)))
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#endif
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@ -324,6 +324,8 @@ MEM_STATIC U32 ZSTD_highbit32(U32 val) /* compress, dictBuilder, decodeCorpus
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return (unsigned)r;
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# elif defined(__GNUC__) && (__GNUC__ >= 3) /* GCC Intrinsic */
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return 31 - __builtin_clz(val);
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# elif defined(__ICCARM__) /* IAR Intrinsic */
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return 31 - __CLZ(val);
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# else /* Software version */
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static const U32 DeBruijnClz[32] = { 0, 9, 1, 10, 13, 21, 2, 29, 11, 14, 16, 18, 22, 25, 3, 30, 8, 12, 20, 28, 15, 17, 24, 7, 19, 27, 23, 6, 26, 5, 4, 31 };
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U32 v = val;
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