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71 Commits (7306ba78d62b55a64f25231df1d5697345a5572e)

Author SHA1 Message Date
Mike Pall 7306ba78d6 Merge branch 'master' into v2.1 2022-01-15 19:42:30 +01:00
Mike Pall c4dfb625ba Bump copyright date. 2022-01-15 19:30:54 +01:00
Mike Pall bb0f241015 Compile table traversals: next(), pairs(), BC_ISNEXT/BC_ITERN. 
Sponsored by OpenResty Inc.
 2021-09-19 17:49:25 +02:00
Mike Pall 986bb406ad Use IR_HIOP for generalized two-register returns. 
Sponsored by OpenResty Inc.
 2021-09-19 17:47:11 +02:00
Mike Pall 9211f0b03b Refactor IR_VLOAD to take an offset. 2021-09-19 17:18:16 +02:00
Mike Pall f2d333c1ac MIPS: Fix trace linking. 2021-09-19 16:09:48 +02:00
Mike Pall 02bcbea8b0 String buffers, part 3c: Add IRBUFHDR_WRITE mode. 
Sponsored by fmad.io.
 2021-07-19 16:46:27 +02:00
Mike Pall 6df650fe3f String buffers, part 3a: Add IR_TMPREF for passing TValues to helpers. 
Sponsored by fmad.io.
 2021-07-19 16:23:12 +02:00
Mike Pall de89c602c2 PPC: Fix GG_State loads. 2021-03-23 00:28:03 +01:00
Mike Pall 1e66d0f9e6 Merge branch 'master' into v2.1 2021-01-02 21:56:07 +01:00
Mike Pall f47c864b01 Bump copyright date. 2021-01-02 21:49:41 +01:00
Mike Pall 2e55a42c07 Merge branch 'master' into v2.1 2020-09-27 17:20:37 +02:00
Mike Pall e8ec6fe996 Prevent patching of the GC exit check branch. 
Reported by Arseny Vakhrushev.
 2020-09-27 16:44:13 +02:00
Mike Pall ff34b48ddd Redesign and harden string interning. 
Up to 40% faster on hash-intensive benchmarks.
With some ideas from Sokolov Yura.
 2020-06-23 03:06:45 +02:00
Mike Pall 8ae5170cdc Improve assertions. 2020-06-15 02:52:00 +02:00
Mike Pall b2307c8ad8 Remove pow() splitting and cleanup backends. 2020-05-23 21:33:01 +02:00
Mike Pall 5655be4546 Cleanup math function compilation and fix inconsistencies. 2020-05-22 04:53:35 +02:00
Mike Pall 03208c8162 Fix math.min()/math.max() inconsistencies. 2020-05-22 03:10:30 +02:00
Mike Pall 87b111f0fe Merge branch 'master' into v2.1 2020-01-20 23:34:21 +01:00
Mike Pall 38a5ed4b43 Bump copyright date. 2020-01-20 23:26:51 +01:00
Mike Pall 71b7bc8834 PPC: Add soft-float support to JIT compiler backend. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
 2017-09-03 23:20:53 +02:00
Mike Pall 71ff7ef8a7 Merge branch 'master' into v2.1 2017-01-17 12:41:05 +01:00
Mike Pall b93a1dd0c8 Bump copyright date to 2017. 2017-01-17 12:35:03 +01:00
Mike Pall e577db52c5 Increase range of GG_State loads via IR_FLOAD with REF_NIL. 
Require 32 bit alignment and store offset/4 instead.
Otherwise this can overflow the 10 bit limit for the FOLD op2 key.
 2016-11-19 19:53:46 +01:00
Mike Pall 786dbb2ebd Add IR_FLOAD with REF_NIL for field loads from GG_State. 
Contributed by Peter Cawley.
 2016-05-21 01:00:49 +02:00
Mike Pall cfa188f134 Move common 32/64 bit in-memory FP constants to jit_State. 
Prerequisite for immovable IR.
Contributed by Peter Cawley.
 2016-05-21 00:02:45 +02:00
Mike Pall 475a6ae33f Merge branch 'master' into v2.1 2016-05-20 20:26:39 +02:00
Mike Pall 37e1e70313 Add guard for obscure aliasing between open upvalues and SSA slots. 
Thanks to Peter Cawley.
 2016-05-20 20:24:06 +02:00
Mike Pall f4231949b5 Merge branch 'master' into v2.1 2016-03-03 12:11:37 +01:00
Mike Pall db1b399af1 Bump copyright date to 2016. 2016-03-03 12:02:22 +01:00
Mike Pall 6cb38f788f Merge branch 'master' into v2.1 2016-02-10 18:53:42 +01:00
Mike Pall a443889677 Don't allocate unused 2nd result register in JIT compiler backend. 2016-02-10 18:51:02 +01:00
Mike Pall 361827c8f9 PPC64: Add build infrastructure. 2015-03-06 03:47:45 +01:00
Mike Pall 0a5045c34e Merge branch 'master' into v2.1 2015-01-06 00:12:45 +01:00
Mike Pall 86913b9bbf Bump copyright date to 2015. 2015-01-05 23:59:31 +01:00
Mike Pall 054e6abe37 Add LJ_FR2 mode: Two-slot frame info. 2015-01-03 15:04:38 +01:00
Mike Pall 7400e2c0cc Merge branch 'master' into v2.1 2014-05-27 15:59:20 +02:00
Mike Pall 49d3157e14 PPC: Fix red zone overflow in machine code generation. 2014-05-27 15:58:04 +02:00
Mike Pall 2863b10956 Merge branch 'master' into v2.1 2014-02-20 15:09:02 +01:00
Mike Pall 2bc63bb6af Prevent BASE register coalescing if parent uses IR_RETF. 2014-02-19 17:09:22 +01:00
Mike Pall a9d4543601 Merge branch 'master' into v2.1 2014-01-16 23:18:34 +01:00
Mike Pall ef59e54820 Bump copyright date to 2014. 2014-01-16 23:10:16 +01:00
Mike Pall d1194a82eb Low-overhead profiler, part 4: JIT compiler support. 2013-09-08 02:53:23 +02:00
Mike Pall 517500ba48 Save currently executing lua_State in g->cur_L. 
This is only a good approximation due to deficiencies in the design of
the Lua/C API. It indicates _some_ valid state that is/was executing.
Also reorder L->cframe stores to achieve a synchronously consistent state.
 2013-08-30 23:38:17 +02:00
Mike Pall f1f7e40318 FFI: Compile VLA/VLS and large cdata allocs with default initialization. 2013-05-24 00:49:02 +02:00
Mike Pall 647cc4613f Merge branch 'master' into v2.1 2013-05-16 20:07:53 +02:00
Mike Pall 0f79d4741f Handle calls with max. args in backends even after SPLIT. 2013-05-16 19:59:38 +02:00
Mike Pall acda75ad2c Refactor CCallInfo representation for split arguments. 2013-05-13 19:49:46 +02:00
Mike Pall a2c78810ca Combine IR instruction dispatch for all assembler backends. 2013-04-22 22:32:41 +02:00
Mike Pall 988e183965 Reorganize generic operations common to all assembler backends. 2013-04-22 17:34:36 +02:00