7306ba78d6
Merge branch 'master' into v2.1
2022-01-15 19:42:30 +01:00
c4dfb625ba
Bump copyright date.
2022-01-15 19:30:54 +01:00
bb0f241015
Compile table traversals: next(), pairs(), BC_ISNEXT/BC_ITERN.
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Sponsored by OpenResty Inc.
2021-09-19 17:49:25 +02:00
986bb406ad
Use IR_HIOP for generalized two-register returns.
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Sponsored by OpenResty Inc.
2021-09-19 17:47:11 +02:00
9211f0b03b
Refactor IR_VLOAD to take an offset.
2021-09-19 17:18:16 +02:00
f2d333c1ac
MIPS: Fix trace linking.
2021-09-19 16:09:48 +02:00
02bcbea8b0
String buffers, part 3c: Add IRBUFHDR_WRITE mode.
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Sponsored by fmad.io.
2021-07-19 16:46:27 +02:00
6df650fe3f
String buffers, part 3a: Add IR_TMPREF for passing TValues to helpers.
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Sponsored by fmad.io.
2021-07-19 16:23:12 +02:00
1e66d0f9e6
Merge branch 'master' into v2.1
2021-01-02 21:56:07 +01:00
f47c864b01
Bump copyright date.
2021-01-02 21:49:41 +01:00
2e55a42c07
Merge branch 'master' into v2.1
2020-09-27 17:20:37 +02:00
e8ec6fe996
Prevent patching of the GC exit check branch.
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Reported by Arseny Vakhrushev.
2020-09-27 16:44:13 +02:00
ff34b48ddd
Redesign and harden string interning.
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Up to 40% faster on hash-intensive benchmarks.
With some ideas from Sokolov Yura.
2020-06-23 03:06:45 +02:00
d333b1a6fe
ARM: Implement FLOAD from GG_State.
2020-06-13 01:12:14 +02:00
8ae5170cdc
Improve assertions.
2020-06-15 02:52:00 +02:00
b2307c8ad8
Remove pow() splitting and cleanup backends.
2020-05-23 21:33:01 +02:00
5655be4546
Cleanup math function compilation and fix inconsistencies.
2020-05-22 04:53:35 +02:00
03208c8162
Fix math.min()/math.max() inconsistencies.
2020-05-22 03:10:30 +02:00
87b111f0fe
Merge branch 'master' into v2.1
2020-01-20 23:34:21 +01:00
38a5ed4b43
Bump copyright date.
2020-01-20 23:26:51 +01:00
178512fab9
Merge branch 'master' into v2.1
2019-04-29 18:04:47 +02:00
9bd5a722be
ARM: Fix GCC 7 -Wimplicit-fallthrough warnings.
2019-04-29 18:02:50 +02:00
5802ab56b6
ARM: Fix condition code check fusion.
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Reported by Qingjun Wei.
2019-04-29 17:38:05 +02:00
71ff7ef8a7
Merge branch 'master' into v2.1
2017-01-17 12:41:05 +01:00
b93a1dd0c8
Bump copyright date to 2017.
2017-01-17 12:35:03 +01:00
786dbb2ebd
Add IR_FLOAD with REF_NIL for field loads from GG_State.
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Contributed by Peter Cawley.
2016-05-21 01:00:49 +02:00
475a6ae33f
Merge branch 'master' into v2.1
2016-05-20 20:26:39 +02:00
37e1e70313
Add guard for obscure aliasing between open upvalues and SSA slots.
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Thanks to Peter Cawley.
2016-05-20 20:24:06 +02:00
f4231949b5
Merge branch 'master' into v2.1
2016-03-03 12:11:37 +01:00
db1b399af1
Bump copyright date to 2016.
2016-03-03 12:02:22 +01:00
6cb38f788f
Merge branch 'master' into v2.1
2016-02-10 18:53:42 +01:00
a443889677
Don't allocate unused 2nd result register in JIT compiler backend.
2016-02-10 18:51:02 +01:00
825dcdc4d1
Generalize LJ_SOFTFP dependencies in lj_asm.c.
2016-02-09 17:29:23 +01:00
0a5045c34e
Merge branch 'master' into v2.1
2015-01-06 00:12:45 +01:00
86913b9bbf
Bump copyright date to 2015.
2015-01-05 23:59:31 +01:00
054e6abe37
Add LJ_FR2 mode: Two-slot frame info.
2015-01-03 15:04:38 +01:00
2863b10956
Merge branch 'master' into v2.1
2014-02-20 15:09:02 +01:00
2bc63bb6af
Prevent BASE register coalescing if parent uses IR_RETF.
2014-02-19 17:09:22 +01:00
a9d4543601
Merge branch 'master' into v2.1
2014-01-16 23:18:34 +01:00
ef59e54820
Bump copyright date to 2014.
2014-01-16 23:10:16 +01:00
d1194a82eb
Low-overhead profiler, part 4: JIT compiler support.
2013-09-08 02:53:23 +02:00
517500ba48
Save currently executing lua_State in g->cur_L.
...
This is only a good approximation due to deficiencies in the design of
the Lua/C API. It indicates _some_ valid state that is/was executing.
Also reorder L->cframe stores to achieve a synchronously consistent state.
2013-08-30 23:38:17 +02:00
92a3cf469c
Merge branch 'master' into v2.1
2013-07-31 01:49:58 +02:00
6a878b0441
ARM: Fix register allocation when rematerializing FPRs.
2013-07-31 01:48:21 +02:00
f1f7e40318
FFI: Compile VLA/VLS and large cdata allocs with default initialization.
2013-05-24 00:49:02 +02:00
647cc4613f
Merge branch 'master' into v2.1
2013-05-16 20:07:53 +02:00
0f79d4741f
Handle calls with max. args in backends even after SPLIT.
2013-05-16 19:59:38 +02:00
acda75ad2c
Refactor CCallInfo representation for split arguments.
2013-05-13 19:49:46 +02:00
a2c78810ca
Combine IR instruction dispatch for all assembler backends.
2013-04-22 22:32:41 +02:00
2ab5e7c5dc
Merge branch 'master' into v2.1
2013-04-22 22:30:33 +02:00
Mike Pall