PPC: Integrate and enable JIT compiler.
Mike Pall
parent
fa9ade356b
commit
0cf8c20be8
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@ -163,7 +163,6 @@
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#define LJ_TARGET_MASKROT 1
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#define LJ_TARGET_UNIFYROT 1 /* Want only IR_BROL. */
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#define LJ_ARCH_NUMMODE LJ_NUMMODE_DUAL_SINGLE
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#define LJ_ARCH_NOJIT 1
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#elif LUAJIT_TARGET == LUAJIT_ARCH_PPCSPE
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@ -161,6 +161,8 @@ IRFLDEF(FLOFS)
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#include "lj_emit_x86.h"
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#elif LJ_TARGET_ARM
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#include "lj_emit_arm.h"
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#elif LJ_TARGET_PPC
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#include "lj_emit_ppc.h"
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#else
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#error "Missing instruction emitter for target CPU"
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#endif
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@ -1205,8 +1207,10 @@ static void asm_loop(ASMState *as)
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#include "lj_asm_x86.h"
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#elif LJ_TARGET_ARM
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#include "lj_asm_arm.h"
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#elif LJ_TARGET_PPC
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#include "lj_asm_ppc.h"
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#else
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#error "Missing instruction emitter for target CPU"
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#error "Missing assembler for target CPU"
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#endif
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/* -- Head of trace ------------------------------------------------------- */
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File diff suppressed because it is too large
Load Diff
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@ -526,9 +526,13 @@ again:
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idx = emitir(IRT(IR_BAND, IRT_INTP), idx, lj_ir_kintp(J, 1));
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sz = lj_ctype_size(cts, (sid = ctype_cid(ct->info)));
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idx = crec_reassoc_ofs(J, idx, &ofs, sz);
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#if LJ_TARGET_ARM || LJ_TARGET_PPC
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/* Hoist base add to allow fusion of index/shift into operands. */
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if (LJ_LIKELY(J->flags & JIT_F_OPT_LOOP) && ofs
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#if LJ_TARGET_ARM
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/* Hoist base add to allow fusion of shifts into operands. */
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if (LJ_LIKELY(J->flags & JIT_F_OPT_LOOP) && ofs && (sz == 1 || sz == 4)) {
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&& (sz == 1 || sz == 4)
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#endif
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) {
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ptr = emitir(IRT(IR_ADD, IRT_PTR), ptr, lj_ir_kintp(J, ofs));
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ofs = 0;
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}
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@ -0,0 +1,232 @@
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/*
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** PPC instruction emitter.
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** Copyright (C) 2005-2011 Mike Pall. See Copyright Notice in luajit.h
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*/
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/* -- Emit basic instructions --------------------------------------------- */
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static void emit_tab(ASMState *as, PPCIns pi, Reg rt, Reg ra, Reg rb)
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{
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*--as->mcp = pi | PPCF_T(rt) | PPCF_A(ra) | PPCF_B(rb);
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}
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#define emit_asb(as, pi, ra, rs, rb) emit_tab(as, (pi), (rs), (ra), (rb))
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#define emit_as(as, pi, ra, rs) emit_tab(as, (pi), (rs), (ra), 0)
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#define emit_ab(as, pi, ra, rb) emit_tab(as, (pi), 0, (ra), (rb))
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static void emit_tai(ASMState *as, PPCIns pi, Reg rt, Reg ra, int32_t i)
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{
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*--as->mcp = pi | PPCF_T(rt) | PPCF_A(ra) | (i & 0xffff);
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}
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#define emit_ti(as, pi, rt, i) emit_tai(as, (pi), (rt), 0, (i))
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#define emit_ai(as, pi, ra, i) emit_tai(as, (pi), 0, (ra), (i))
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#define emit_asi(as, pi, ra, rs, i) emit_tai(as, (pi), (rs), (ra), (i))
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#define emit_fab(as, pi, rf, ra, rb) \
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emit_tab(as, (pi), (rf)&31, (ra)&31, (rb)&31)
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#define emit_fb(as, pi, rf, rb) emit_tab(as, (pi), (rf)&31, 0, (rb)&31)
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#define emit_fac(as, pi, rf, ra, rc) \
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emit_tab(as, (pi) | PPCF_C((rc) & 31), (rf)&31, (ra)&31, 0)
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#define emit_facb(as, pi, rf, ra, rc, rb) \
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emit_tab(as, (pi) | PPCF_C((rc) & 31), (rf)&31, (ra)&31, (rb)&31)
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#define emit_fai(as, pi, rf, ra, i) emit_tai(as, (pi), (rf)&31, (ra), (i))
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static void emit_rot(ASMState *as, PPCIns pi, Reg ra, Reg rs,
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int32_t n, int32_t b, int32_t e)
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{
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*--as->mcp = pi | PPCF_T(rs) | PPCF_A(ra) | PPCF_B(n) |
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PPCF_MB(b) | PPCF_ME(e);
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}
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static void emit_slwi(ASMState *as, Reg ra, Reg rs, int32_t n)
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{
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lua_assert(n >= 0 && n < 32);
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emit_rot(as, PPCI_RLWINM, ra, rs, n, 0, 31-n);
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}
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static void emit_rotlwi(ASMState *as, Reg ra, Reg rs, int32_t n)
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{
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lua_assert(n >= 0 && n < 32);
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emit_rot(as, PPCI_RLWINM, ra, rs, n, 0, 31);
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}
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/* -- Emit loads/stores --------------------------------------------------- */
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/* Prefer rematerialization of BASE/L from global_State over spills. */
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#define emit_canremat(ref) ((ref) <= REF_BASE)
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/* Try to find a one step delta relative to another constant. */
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static int emit_kdelta1(ASMState *as, Reg t, int32_t i)
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{
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RegSet work = ~as->freeset & RSET_GPR;
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while (work) {
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Reg r = rset_picktop(work);
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IRRef ref = regcost_ref(as->cost[r]);
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lua_assert(r != t);
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if (ref < ASMREF_L) {
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int32_t delta = i - (ra_iskref(ref) ? ra_krefk(as, ref) : IR(ref)->i);
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if (checki16(delta)) {
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emit_tai(as, PPCI_ADDI, t, r, delta);
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return 1;
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}
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}
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rset_clear(work, r);
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}
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return 0; /* Failed. */
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}
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/* Load a 32 bit constant into a GPR. */
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static void emit_loadi(ASMState *as, Reg r, int32_t i)
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{
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if (checki16(i)) {
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emit_ti(as, PPCI_LI, r, i);
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} else {
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if ((i & 0xffff)) {
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int32_t jgl = i32ptr(J2G(as->J));
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if ((uint32_t)(i-jgl) < 65536) {
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emit_tai(as, PPCI_ADDI, r, RID_JGL, i-jgl-32768);
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return;
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} else if (emit_kdelta1(as, r, i)) {
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return;
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}
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emit_asi(as, PPCI_ORI, r, r, i);
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}
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emit_ti(as, PPCI_LIS, r, (i >> 16));
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}
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}
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#define emit_loada(as, r, addr) emit_loadi(as, (r), i32ptr((addr)))
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static Reg ra_allock(ASMState *as, int32_t k, RegSet allow);
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/* Get/set from constant pointer. */
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static void emit_lsptr(ASMState *as, PPCIns pi, Reg r, void *p, RegSet allow)
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{
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int32_t jgl = i32ptr(J2G(as->J));
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int32_t i = i32ptr(p);
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Reg base;
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if ((uint32_t)(i-jgl) < 65536) {
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i = i-jgl-32768;
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base = RID_JGL;
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} else {
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base = ra_allock(as, i-(int16_t)i, allow);
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}
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emit_tai(as, pi, r, base, i);
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}
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#define emit_loadn(as, r, tv) \
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emit_lsptr(as, PPCI_LFD, ((r) & 31), (void *)(tv), RSET_GPR)
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/* Get/set global_State fields. */
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static void emit_lsglptr(ASMState *as, PPCIns pi, Reg r, int32_t ofs)
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{
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emit_tai(as, pi, r, RID_JGL, ofs-32768);
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}
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#define emit_getgl(as, r, field) \
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emit_lsglptr(as, PPCI_LWZ, (r), (int32_t)offsetof(global_State, field))
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#define emit_setgl(as, r, field) \
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emit_lsglptr(as, PPCI_STW, (r), (int32_t)offsetof(global_State, field))
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/* Trace number is determined from per-trace exit stubs. */
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#define emit_setvmstate(as, i) UNUSED(i)
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/* -- Emit control-flow instructions -------------------------------------- */
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/* Label for internal jumps. */
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typedef MCode *MCLabel;
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/* Return label pointing to current PC. */
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#define emit_label(as) ((as)->mcp)
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static void emit_condbranch(ASMState *as, PPCIns pi, PPCCC cc, MCode *target)
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{
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MCode *p = as->mcp;
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ptrdiff_t delta = ((char *)target - (char *)p) + 4;
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lua_assert(((delta + 0x8000) >> 16) == 0);
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pi ^= (delta & 0x8000) * (PPCF_Y/0x8000);
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*--p = pi | PPCF_CC(cc) | ((uint32_t)delta & 0xffffu);
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as->mcp = p;
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}
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static void emit_call(ASMState *as, void *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = (char *)target - (char *)p;
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if ((((delta>>2) + 0x00800000) >> 24) == 0) {
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*p = PPCI_BL | (delta & 0x03fffffcu);
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} else { /* Target out of range: need indirect call. Don't use arg reg. */
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RegSet allow = RSET_GPR & ~RSET_RANGE(RID_R0, REGARG_LASTGPR+1);
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Reg r = ra_allock(as, i32ptr(target), allow);
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*p = PPCI_BCTRL;
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p[-1] = PPCI_MTCTR | PPCF_T(r);
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as->mcp = p-1;
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}
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}
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/* -- Emit generic operations --------------------------------------------- */
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#define emit_mr(as, dst, src) \
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emit_asb(as, PPCI_MR, (dst), (src), (src))
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/* Generic move between two regs. */
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static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
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{
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UNUSED(ir);
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if (dst < RID_MAX_GPR)
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emit_mr(as, dst, src);
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else
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emit_fb(as, PPCI_FMR, dst, src);
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}
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/* Generic load of register from stack slot. */
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static void emit_spload(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
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{
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if (r < RID_MAX_GPR)
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emit_tai(as, PPCI_LWZ, r, RID_SP, ofs);
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else
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emit_fai(as, irt_isnum(ir->t) ? PPCI_LFD : PPCI_LFS, r, RID_SP, ofs);
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}
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/* Generic store of register to stack slot. */
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static void emit_spstore(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
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{
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if (r < RID_MAX_GPR)
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emit_tai(as, PPCI_STW, r, RID_SP, ofs);
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else
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emit_fai(as, irt_isnum(ir->t) ? PPCI_STFD : PPCI_STFS, r, RID_SP, ofs);
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}
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/* Emit a compare (for equality) with a constant operand. */
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static void emit_cmpi(ASMState *as, Reg r, int32_t k)
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{
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if (checki16(k)) {
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emit_ai(as, PPCI_CMPWI, r, k);
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} else if (checku16(k)) {
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emit_ai(as, PPCI_CMPLWI, r, k);
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} else {
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emit_ai(as, PPCI_CMPLWI, RID_TMP, k);
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emit_asi(as, PPCI_XORIS, RID_TMP, r, (k >> 16));
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}
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}
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/* Add offset to pointer. */
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static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
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{
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if (ofs) {
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emit_tai(as, PPCI_ADDI, r, r, ofs);
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if (!checki16(ofs))
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emit_tai(as, PPCI_ADDIS, r, r, (ofs + 32768) >> 16);
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}
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}
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static void emit_spsub(ASMState *as, int32_t ofs)
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{
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if (ofs) {
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emit_tai(as, PPCI_STWU, RID_TMP, RID_SP, -ofs);
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emit_tai(as, PPCI_ADDI, RID_TMP, RID_SP,
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CFRAME_SIZE + (as->parent ? as->parent->spadjust : 0));
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}
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}
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@ -50,21 +50,30 @@ typedef uint32_t RegSP;
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/* -- Register sets ------------------------------------------------------- */
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/* Bitset for registers. 32 registers suffice right now.
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/* Bitset for registers. 32 registers suffice for most architectures.
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** Note that one set holds bits for both GPRs and FPRs.
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*/
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#if LJ_TARGET_PPC
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typedef uint64_t RegSet;
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#else
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typedef uint32_t RegSet;
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#endif
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#define RID2RSET(r) (((RegSet)1) << (r))
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#define RSET_EMPTY 0
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#define RSET_EMPTY ((RegSet)0)
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#define RSET_RANGE(lo, hi) ((RID2RSET((hi)-(lo))-1) << (lo))
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#define rset_test(rs, r) (((rs) >> (r)) & 1)
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#define rset_set(rs, r) (rs |= RID2RSET(r))
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#define rset_clear(rs, r) (rs &= ~RID2RSET(r))
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#define rset_exclude(rs, r) (rs & ~RID2RSET(r))
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#if LJ_TARGET_PPC
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#define rset_picktop(rs) ((Reg)(__builtin_clzll(rs)^63))
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#define rset_pickbot(rs) ((Reg)__builtin_ctzll(rs))
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#else
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#define rset_picktop(rs) ((Reg)lj_fls(rs))
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#define rset_pickbot(rs) ((Reg)lj_ffs(rs))
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#endif
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/* -- Register allocation cost -------------------------------------------- */
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@ -127,6 +136,8 @@ typedef uint32_t RegCost;
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#include "lj_target_x86.h"
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#elif LJ_TARGET_ARM
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#include "lj_target_arm.h"
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#elif LJ_TARGET_PPC
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#include "lj_target_ppc.h"
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#else
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#error "Missing include for target CPU"
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#endif
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@ -0,0 +1,273 @@
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/*
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** Definitions for PPC CPUs.
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** Copyright (C) 2005-2011 Mike Pall. See Copyright Notice in luajit.h
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*/
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#ifndef _LJ_TARGET_PPC_H
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#define _LJ_TARGET_PPC_H
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/* -- Registers IDs ------------------------------------------------------- */
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#define GPRDEF(_) \
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_(R0) _(SP) _(SYS1) _(R3) _(R4) _(R5) _(R6) _(R7) \
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_(R8) _(R9) _(R10) _(R11) _(R12) _(SYS2) _(R14) _(R15) \
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_(R16) _(R17) _(R18) _(R19) _(R20) _(R21) _(R22) _(R23) \
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_(R24) _(R25) _(R26) _(R27) _(R28) _(R29) _(R30) _(R31)
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#define FPRDEF(_) \
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_(F0) _(F1) _(F2) _(F3) _(F4) _(F5) _(F6) _(F7) \
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_(F8) _(F9) _(F10) _(F11) _(F12) _(F13) _(F14) _(F15) \
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_(F16) _(F17) _(F18) _(F19) _(F20) _(F21) _(F22) _(F23) \
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_(F24) _(F25) _(F26) _(F27) _(F28) _(F29) _(F30) _(F31)
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#define VRIDDEF(_)
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#define RIDENUM(name) RID_##name,
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enum {
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GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
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FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
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RID_MAX,
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RID_TMP = RID_R0,
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/* Calling conventions. */
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RID_RET = RID_R3,
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RID_RETHI = RID_R3,
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RID_RETLO = RID_R4,
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RID_FPRET = RID_F1,
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/* These definitions must match with the *.dasc file(s): */
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RID_BASE = RID_R14, /* Interpreter BASE. */
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RID_LPC = RID_R16, /* Interpreter PC. */
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RID_DISPATCH = RID_R17, /* Interpreter DISPATCH table. */
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RID_LREG = RID_R18, /* Interpreter L. */
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RID_JGL = RID_R31, /* On-trace: global_State + 32768. */
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/* Register ranges [min, max) and number of registers. */
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RID_MIN_GPR = RID_R0,
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RID_MAX_GPR = RID_R31+1,
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RID_MIN_FPR = RID_F0,
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RID_MAX_FPR = RID_F31+1,
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RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
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RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR
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};
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#define RID_NUM_KREF RID_NUM_GPR
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#define RID_MIN_KREF RID_R0
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/* -- Register sets ------------------------------------------------------- */
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/* Make use of all registers, except TMP, SP, SYS1, SYS2 and JGL. */
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#define RSET_FIXED \
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(RID2RSET(RID_TMP)|RID2RSET(RID_SP)|RID2RSET(RID_SYS1)|\
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RID2RSET(RID_SYS2)|RID2RSET(RID_JGL))
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#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED)
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#define RSET_FPR RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR)
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#define RSET_ALL (RSET_GPR|RSET_FPR)
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#define RSET_INIT RSET_ALL
|
||||
|
||||
#define RSET_SCRATCH_GPR (RSET_RANGE(RID_R3, RID_R12+1))
|
||||
#define RSET_SCRATCH_FPR (RSET_RANGE(RID_F0, RID_F13+1))
|
||||
#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
|
||||
#define REGARG_FIRSTGPR RID_R3
|
||||
#define REGARG_LASTGPR RID_R10
|
||||
#define REGARG_NUMGPR 8
|
||||
#define REGARG_FIRSTFPR RID_F1
|
||||
#define REGARG_LASTFPR RID_F8
|
||||
#define REGARG_NUMFPR 8
|
||||
|
||||
/* -- Spill slots --------------------------------------------------------- */
|
||||
|
||||
/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
|
||||
**
|
||||
** SPS_FIXED: Available fixed spill slots in interpreter frame.
|
||||
** This definition must match with the *.dasc file(s).
|
||||
**
|
||||
** SPS_FIRST: First spill slot for general use.
|
||||
** [sp+12] tmplo word \
|
||||
** [sp+ 8] tmphi word / tmp dword, parameter area for callee
|
||||
** [sp+ 4] tmpw, LR of callee
|
||||
** [sp+ 0] stack chain
|
||||
*/
|
||||
#define SPS_FIXED 7
|
||||
#define SPS_FIRST 4
|
||||
|
||||
/* Stack offsets for temporary slots. Used for FP<->int conversions etc. */
|
||||
#define SPOFS_TMPW 4
|
||||
#define SPOFS_TMP 8
|
||||
#define SPOFS_TMPHI 8
|
||||
#define SPOFS_TMPLO 12
|
||||
|
||||
#define sps_scale(slot) (4 * (int32_t)(slot))
|
||||
#define sps_align(slot) (((slot) - SPS_FIXED + 3) & ~3)
|
||||
|
||||
/* -- Exit state ---------------------------------------------------------- */
|
||||
|
||||
/* This definition must match with the *.dasc file(s). */
|
||||
typedef struct {
|
||||
lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
|
||||
int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
|
||||
int32_t spill[256]; /* Spill slots. */
|
||||
} ExitState;
|
||||
|
||||
/* Highest exit + 1 indicates stack check. */
|
||||
#define EXITSTATE_CHECKEXIT 1
|
||||
|
||||
/* Return the address of a per-trace exit stub. */
|
||||
static LJ_AINLINE MCode *exitstub_trace_addr(GCtrace *T, ExitNo exitno)
|
||||
{
|
||||
/* Keep this in-sync with asm_exitstub_*. */
|
||||
MCode *p = (MCode *)((char *)T->mcode + T->szmcode);
|
||||
while (*p == 0x60000000) p++; /* Skip PPCI_NOP. */
|
||||
return p + 3 + exitno;
|
||||
}
|
||||
|
||||
/* -- Instructions -------------------------------------------------------- */
|
||||
|
||||
/* Instruction fields. */
|
||||
#define PPCF_CC(cc) ((((cc) & 3) << 16) | (((cc) & 4) << 22))
|
||||
#define PPCF_T(r) ((r) << 21)
|
||||
#define PPCF_A(r) ((r) << 16)
|
||||
#define PPCF_B(r) ((r) << 11)
|
||||
#define PPCF_C(r) ((r) << 6)
|
||||
#define PPCF_MB(n) ((n) << 6)
|
||||
#define PPCF_ME(n) ((n) << 1)
|
||||
#define PPCF_Y 0x00200000
|
||||
#define PPCF_DOT 0x00000001
|
||||
|
||||
typedef enum PPCIns {
|
||||
/* Integer instructions. */
|
||||
PPCI_MR = 0x7c000378,
|
||||
PPCI_NOP = 0x60000000,
|
||||
|
||||
PPCI_LI = 0x38000000,
|
||||
PPCI_LIS = 0x3c000000,
|
||||
|
||||
PPCI_ADD = 0x7c000214,
|
||||
PPCI_ADDC = 0x7c000014,
|
||||
PPCI_ADDO = 0x7c000614,
|
||||
PPCI_ADDE = 0x7c000114,
|
||||
PPCI_ADDZE = 0x7c000194,
|
||||
PPCI_ADDME = 0x7c0001d4,
|
||||
PPCI_ADDI = 0x38000000,
|
||||
PPCI_ADDIS = 0x3c000000,
|
||||
PPCI_ADDIC = 0x30000000,
|
||||
PPCI_ADDICDOT = 0x34000000,
|
||||
|
||||
PPCI_SUBF = 0x7c000050,
|
||||
PPCI_SUBFC = 0x7c000010,
|
||||
PPCI_SUBFO = 0x7c000450,
|
||||
PPCI_SUBFE = 0x7c000110,
|
||||
PPCI_SUBFZE = 0x7c000190,
|
||||
PPCI_SUBFME = 0x7c0001d0,
|
||||
PPCI_SUBFIC = 0x20000000,
|
||||
|
||||
PPCI_NEG = 0x7c0000d0,
|
||||
|
||||
PPCI_AND = 0x7c000038,
|
||||
PPCI_ANDC = 0x7c000078,
|
||||
PPCI_NAND = 0x7c0003b8,
|
||||
PPCI_ANDIDOT = 0x70000000,
|
||||
PPCI_ANDISDOT = 0x74000000,
|
||||
|
||||
PPCI_OR = 0x7c000378,
|
||||
PPCI_NOR = 0x7c0000f8,
|
||||
PPCI_ORI = 0x60000000,
|
||||
PPCI_ORIS = 0x64000000,
|
||||
|
||||
PPCI_XOR = 0x7c000278,
|
||||
PPCI_EQV = 0x7c000238,
|
||||
PPCI_XORI = 0x68000000,
|
||||
PPCI_XORIS = 0x6c000000,
|
||||
|
||||
PPCI_CMPW = 0x7c000000,
|
||||
PPCI_CMPLW = 0x7c000040,
|
||||
PPCI_CMPWI = 0x2c000000,
|
||||
PPCI_CMPLWI = 0x28000000,
|
||||
|
||||
PPCI_MULLW = 0x7c0001d6,
|
||||
PPCI_MULLI = 0x1c000000,
|
||||
PPCI_MULLWO = 0x7c0005d6,
|
||||
|
||||
PPCI_EXTSB = 0x7c000774,
|
||||
PPCI_EXTSH = 0x7c000734,
|
||||
|
||||
PPCI_SLW = 0x7c000030,
|
||||
PPCI_SRW = 0x7c000430,
|
||||
PPCI_SRAW = 0x7c000630,
|
||||
PPCI_SRAWI = 0x7c000670,
|
||||
|
||||
PPCI_RLWNM = 0x5c000000,
|
||||
PPCI_RLWINM = 0x54000000,
|
||||
PPCI_RLWIMI = 0x50000000,
|
||||
|
||||
PPCI_B = 0x48000000,
|
||||
PPCI_BL = 0x48000001,
|
||||
PPCI_BC = 0x40800000,
|
||||
PPCI_BCL = 0x40800001,
|
||||
PPCI_BCTR = 0x4e800420,
|
||||
PPCI_BCTRL = 0x4e800421,
|
||||
|
||||
PPCI_CRANDC = 0x4c000102,
|
||||
PPCI_CRAND = 0x4c000202,
|
||||
PPCI_CRORC = 0x4c000342,
|
||||
PPCI_CROR = 0x4c000382,
|
||||
|
||||
PPCI_MFLR = 0x7c0802a6,
|
||||
PPCI_MTCTR = 0x7c0903a6,
|
||||
|
||||
PPCI_MCRXR = 0x7c000400,
|
||||
|
||||
/* Load/store instructions. */
|
||||
PPCI_LWZ = 0x80000000,
|
||||
PPCI_LBZ = 0x88000000,
|
||||
PPCI_STW = 0x90000000,
|
||||
PPCI_STB = 0x98000000,
|
||||
PPCI_LHZ = 0xa0000000,
|
||||
PPCI_LHA = 0xa8000000,
|
||||
PPCI_STH = 0xb0000000,
|
||||
|
||||
PPCI_STWU = 0x94000000,
|
||||
|
||||
PPCI_LFS = 0xc0000000,
|
||||
PPCI_LFD = 0xc8000000,
|
||||
PPCI_STFS = 0xd0000000,
|
||||
PPCI_STFD = 0xd8000000,
|
||||
|
||||
PPCI_LWZX = 0x7c00002e,
|
||||
PPCI_LBZX = 0x7c0000ae,
|
||||
PPCI_STWX = 0x7c00012e,
|
||||
PPCI_STBX = 0x7c0001ae,
|
||||
PPCI_LHZX = 0x7c00022e,
|
||||
PPCI_LHAX = 0x7c0002ae,
|
||||
PPCI_STHX = 0x7c00032e,
|
||||
|
||||
PPCI_LFSX = 0x7c00042e,
|
||||
PPCI_LFDX = 0x7c0004ae,
|
||||
PPCI_STFSX = 0x7c00052e,
|
||||
PPCI_STFDX = 0x7c0005ae,
|
||||
|
||||
/* FP instructions. */
|
||||
PPCI_FMR = 0xfc000090,
|
||||
PPCI_FNEG = 0xfc000050,
|
||||
PPCI_FABS = 0xfc000210,
|
||||
|
||||
PPCI_FRSP = 0xfc000018,
|
||||
PPCI_FCTIWZ = 0xfc00001e,
|
||||
|
||||
PPCI_FADD = 0xfc00002a,
|
||||
PPCI_FSUB = 0xfc000028,
|
||||
PPCI_FMUL = 0xfc000032,
|
||||
PPCI_FDIV = 0xfc000024,
|
||||
|
||||
PPCI_FMADD = 0xfc00003a,
|
||||
PPCI_FMSUB = 0xfc000038,
|
||||
PPCI_FNMSUB = 0xfc00003c,
|
||||
|
||||
PPCI_FCMPU = 0xfc000000,
|
||||
PPCI_FSEL = 0xfc00002e,
|
||||
} PPCIns;
|
||||
|
||||
typedef enum PPCCC {
|
||||
CC_GE, CC_LE, CC_NE, CC_NS, CC_LT, CC_GT, CC_EQ, CC_SO
|
||||
} PPCCC;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue