attache: add preliminary communcations between the Z80 and 8086.
mahlemiut
parent
a472219f9e
commit
24fc3d9f83
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@ -59,7 +59,8 @@
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* - Keyboard repeat
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* - Get at least some of the system tests to pass
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* - and probably lots more I've forgotten, too.
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* - implement Z80-8086 comms on the 8:16
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* - improve Z80-8086 comms on the 8:16, saving a file to the RAM disk under CP/M often ends in deadlock.
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* - add Z8530 SCC and TMS9914A GPIB to the 8:16. These are optional devices, so aren't strictly required at this stage.
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*
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*/
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@ -75,10 +76,10 @@
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#include "machine/z80ctc.h"
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#include "machine/z80sio.h"
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#include "machine/z80pio.h"
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#include "machine/i8255.h"
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#include "cpu/i86/i86.h"
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#include "sound/ay8910.h"
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#include "video/tms9927.h"
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#include "screen.h"
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#include "softlist.h"
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#include "speaker.h"
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@ -233,10 +234,35 @@ class attache816_state : public attache_state
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public:
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attache816_state(const machine_config &mconfig, device_type type, const char *tag)
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: attache_state(mconfig, type, tag),
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m_extcpu(*this,"extcpu")
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m_extcpu(*this,"extcpu"),
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m_ppi(*this,"ppi"),
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m_comms_val(0),
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m_x86_irq_enable(0),
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m_z80_rx_ready(false),
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m_z80_tx_ready(false)
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{ }
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DECLARE_WRITE8_MEMBER(x86_comms_w);
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DECLARE_READ8_MEMBER(x86_comms_r);
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DECLARE_WRITE8_MEMBER(x86_irq_enable);
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DECLARE_WRITE8_MEMBER(x86_iobf_enable_w);
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DECLARE_READ8_MEMBER(z80_comms_r);
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DECLARE_WRITE8_MEMBER(z80_comms_w);
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DECLARE_READ8_MEMBER(z80_comms_status_r);
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DECLARE_WRITE8_MEMBER(z80_comms_ctrl_w);
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DECLARE_WRITE_LINE_MEMBER(ppi_irq);
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DECLARE_WRITE_LINE_MEMBER(x86_dsr);
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virtual void machine_reset() override;
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private:
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required_device<cpu_device> m_extcpu;
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required_device<i8255_device> m_ppi;
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uint8_t m_comms_val;
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uint8_t m_x86_irq_enable;
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bool m_z80_rx_ready;
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bool m_z80_tx_ready;
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};
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// Attributes (based on schematics):
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@ -767,6 +793,111 @@ WRITE_LINE_MEMBER( attache_state::fdc_dack_w )
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{
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}
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/*
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* Z80 <-> 8086 communication
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*/
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WRITE8_MEMBER(attache816_state::x86_comms_w)
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{
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m_comms_val = data;
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m_z80_rx_ready = false;
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machine().scheduler().synchronize();
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logerror("x86 writes %02x to comms\n",data);
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}
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READ8_MEMBER(attache816_state::x86_comms_r)
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{
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m_z80_tx_ready = false;
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logerror("x86 reads %02x from comms\n",m_comms_val);
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machine().scheduler().synchronize();
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return m_comms_val;
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}
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// PPI Port B - IRQ enable
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// bit 0: i8255A PPI
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// bit 1: TMS9914A GPIB
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// bit 2: Z8530 SCC
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// bit 3: 8087 FPU
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// bit 4: enable WAIT logic
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// bit 5: enable high-resolution graphics
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WRITE8_MEMBER(attache816_state::x86_irq_enable)
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{
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m_x86_irq_enable = data;
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}
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WRITE8_MEMBER(attache816_state::x86_iobf_enable_w)
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{
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switch(offset)
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{
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case 0x00:
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m_ppi->pc6_w(0);
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break;
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case 0x01:
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m_ppi->pc6_w(1);
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break;
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case 0x04:
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m_ppi->pc4_w(0);
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break;
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case 0x05:
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m_ppi->pc4_w(1);
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break;
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default:
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logerror("Invalid x86 IRQ enable write offset %02x data %02x\n",offset,data);
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}
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}
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READ8_MEMBER(attache816_state::z80_comms_r)
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{
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m_z80_rx_ready = true;
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m_ppi->pc6_w(0);
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logerror("z80 reads %02x from comms\n",m_comms_val);
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machine().scheduler().synchronize();
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return m_comms_val;
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}
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WRITE8_MEMBER(attache816_state::z80_comms_w)
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{
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m_comms_val = data;
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logerror("z80 writes %02x to comms\n",data);
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m_z80_tx_ready = true;
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m_ppi->pc4_w(0);
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machine().scheduler().synchronize();
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// m_ppi->write(space,0,data);
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}
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// Z80 comms status
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// bit 0: set if no data is ready
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// bit 1: set if ready to accept data
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READ8_MEMBER(attache816_state::z80_comms_status_r)
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{
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uint8_t ret = 0xf0; // low nibble always high?
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if(m_z80_rx_ready)
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ret |= 0x01;
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if(m_z80_tx_ready)
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ret |= 0x02;
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return ret;
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}
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// Z80 comms controller
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// bit 0: Reset 8086
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WRITE8_MEMBER(attache816_state::z80_comms_ctrl_w)
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{
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m_extcpu->set_input_line(INPUT_LINE_RESET,(data & 0x01) ? ASSERT_LINE : CLEAR_LINE);
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}
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WRITE_LINE_MEMBER(attache816_state::ppi_irq)
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{
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if(m_x86_irq_enable & 0x01)
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m_extcpu->set_input_line_and_vector(0,state,0x03);
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}
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WRITE_LINE_MEMBER(attache816_state::x86_dsr)
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{
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// TODO: /DSR to Z8530 SCC
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}
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static ADDRESS_MAP_START( attache_map, AS_PROGRAM, 8, attache_state)
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AM_RANGE(0x0000,0x1fff) AM_RAMBANK("bank1")
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AM_RANGE(0x2000,0x3fff) AM_RAMBANK("bank2")
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@ -790,9 +921,9 @@ static ADDRESS_MAP_START( attache_io, AS_IO, 8, attache_state)
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AM_RANGE(0xff, 0xff) AM_READWRITE(memmap_r, memmap_w) AM_MIRROR(0xff00)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( attache816_io, AS_IO, 8, attache_state)
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// 0xb8 - 8086 comms port (connects to PPI port A)
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// 0xb9 - Status/Control
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static ADDRESS_MAP_START( attache816_io, AS_IO, 8, attache816_state)
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AM_RANGE(0xb8, 0xb8) AM_READWRITE(z80_comms_status_r, z80_comms_ctrl_w) AM_MIRROR(0xff00)
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AM_RANGE(0xb9, 0xb9) AM_READWRITE(z80_comms_r, z80_comms_w) AM_MIRROR(0xff00)
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AM_RANGE(0xe0, 0xed) AM_DEVREADWRITE("dma",am9517a_device,read,write) AM_MIRROR(0xff00)
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AM_RANGE(0xee, 0xee) AM_WRITE(display_command_w) AM_MIRROR(0xff00)
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AM_RANGE(0xef, 0xef) AM_READWRITE(dma_mask_r, dma_mask_w) AM_MIRROR(0xff00)
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@ -804,17 +935,17 @@ static ADDRESS_MAP_START( attache816_io, AS_IO, 8, attache_state)
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AM_RANGE(0xff, 0xff) AM_READWRITE(memmap_r, memmap_w) AM_MIRROR(0xff00)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( attache_x86_map, AS_PROGRAM, 16, attache_state)
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static ADDRESS_MAP_START( attache_x86_map, AS_PROGRAM, 16, attache816_state)
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AM_RANGE(0x00000, 0x3ffff) AM_RAM
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AM_RANGE(0xb0000, 0xbffff) AM_NOP // triggers IRQ?
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AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("x86bios",0x0000)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( attache_x86_io, AS_IO, 16, attache_state)
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// 0x100-0x104 - i8255 PPI
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// 0x108/9 - Set/Clear IBF IRQ enable
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// 0x10c/d - Set/Clear OBF IRQ enable
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AM_RANGE(0x104, 0x105) AM_NOP
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static ADDRESS_MAP_START( attache_x86_io, AS_IO, 16, attache816_state)
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AM_RANGE(0x100, 0x107) AM_DEVREADWRITE8("ppi",i8255_device,read,write,0x00ff)
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AM_RANGE(0x108, 0x10d) AM_WRITE8(x86_iobf_enable_w,0xffff);
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// 0x140/2/4/6 - Z8530 SCC serial
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// 0x180/2/4/6/8/a/c/e - GPIB (TMS9914A)
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ADDRESS_MAP_END
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static INPUT_PORTS_START(attache)
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@ -963,6 +1094,11 @@ void attache_state::machine_reset()
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m_kb_bitpos = 0;
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}
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void attache816_state::machine_reset()
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{
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attache_state::machine_reset();
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}
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static MACHINE_CONFIG_START( attache )
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MCFG_CPU_ADD("maincpu",Z80,XTAL_8MHz / 2)
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MCFG_CPU_PROGRAM_MAP(attache_map)
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@ -1062,6 +1198,13 @@ static MACHINE_CONFIG_START( attache816 )
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MCFG_DEVICE_ADD("ctc", Z80CTC, XTAL_8MHz / 4)
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MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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MCFG_DEVICE_ADD("ppi", I8255A, 0)
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MCFG_I8255_OUT_PORTA_CB(WRITE8(attache816_state, x86_comms_w))
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MCFG_I8255_IN_PORTA_CB(READ8(attache816_state, x86_comms_r))
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MCFG_I8255_OUT_PORTB_CB(WRITE8(attache816_state, x86_irq_enable))
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MCFG_I8255_OUT_PORTC_CB(WRITELINE(attache816_state, x86_dsr)) MCFG_DEVCB_BIT(0)
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MCFG_DEVCB_CHAIN_OUTPUT(WRITELINE(attache816_state, ppi_irq)) MCFG_DEVCB_BIT(7) MCFG_DEVCB_INVERT
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MCFG_DEVICE_ADD("dma", AM9517A, XTAL_8MHz / 4)
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MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(attache_state, hreq_w))
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