215 lines
8.8 KiB
C++
215 lines
8.8 KiB
C++
/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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* vim: set ts=8 sts=4 et sw=4 tw=99:
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef jit_mips32_Assembler_mips32_h
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#define jit_mips32_Assembler_mips32_h
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#include "jit/mips-shared/Assembler-mips-shared.h"
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#include "jit/mips32/Architecture-mips32.h"
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namespace js {
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namespace jit {
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static constexpr Register CallTempReg4 = t4;
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static constexpr Register CallTempReg5 = t5;
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static constexpr Register CallTempNonArgRegs[] = { t0, t1, t2, t3, t4 };
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static const uint32_t NumCallTempNonArgRegs = mozilla::ArrayLength(CallTempNonArgRegs);
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class ABIArgGenerator
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{
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unsigned usedArgSlots_;
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unsigned firstArgFloatSize_;
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// Note: This is not compliant with the system ABI. The Lowering phase
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// expects to lower an MWasmParameter to only one register.
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bool useGPRForFloats_;
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ABIArg current_;
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public:
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ABIArgGenerator();
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ABIArg next(MIRType argType);
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ABIArg& current() { return current_; }
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void enforceO32ABI() {
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useGPRForFloats_ = true;
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}
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uint32_t stackBytesConsumedSoFar() const {
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if (usedArgSlots_ <= 4)
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return ShadowStackSpace;
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return usedArgSlots_ * sizeof(intptr_t);
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}
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};
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static constexpr Register ABINonArgReg0 = t0;
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static constexpr Register ABINonArgReg1 = t1;
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static constexpr Register ABINonArgReg2 = t2;
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static constexpr Register ABINonArgReturnReg0 = t0;
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static constexpr Register ABINonArgReturnReg1 = t1;
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// TLS pointer argument register for WebAssembly functions. This must not alias
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// any other register used for passing function arguments or return values.
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// Preserved by WebAssembly functions.
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static constexpr Register WasmTlsReg = s5;
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// Registers used for asm.js/wasm table calls. These registers must be disjoint
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// from the ABI argument registers, WasmTlsReg and each other.
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static constexpr Register WasmTableCallScratchReg = ABINonArgReg0;
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static constexpr Register WasmTableCallSigReg = ABINonArgReg1;
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static constexpr Register WasmTableCallIndexReg = ABINonArgReg2;
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static constexpr Register JSReturnReg_Type = a3;
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static constexpr Register JSReturnReg_Data = a2;
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static constexpr Register64 ReturnReg64(InvalidReg, InvalidReg);
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static constexpr FloatRegister ReturnFloat32Reg = { FloatRegisters::f0, FloatRegister::Single };
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static constexpr FloatRegister ReturnDoubleReg = { FloatRegisters::f0, FloatRegister::Double };
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static constexpr FloatRegister ScratchFloat32Reg = { FloatRegisters::f18, FloatRegister::Single };
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static constexpr FloatRegister ScratchDoubleReg = { FloatRegisters::f18, FloatRegister::Double };
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static constexpr FloatRegister SecondScratchFloat32Reg = { FloatRegisters::f16, FloatRegister::Single };
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static constexpr FloatRegister SecondScratchDoubleReg = { FloatRegisters::f16, FloatRegister::Double };
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// Registers used in the GenerateFFIIonExit Disable Activation block.
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// None of these may be the second scratch register (t8).
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static constexpr Register WasmIonExitRegReturnData = JSReturnReg_Data;
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static constexpr Register WasmIonExitRegReturnType = JSReturnReg_Type;
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static constexpr FloatRegister f0 = { FloatRegisters::f0, FloatRegister::Double };
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static constexpr FloatRegister f2 = { FloatRegisters::f2, FloatRegister::Double };
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static constexpr FloatRegister f4 = { FloatRegisters::f4, FloatRegister::Double };
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static constexpr FloatRegister f6 = { FloatRegisters::f6, FloatRegister::Double };
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static constexpr FloatRegister f8 = { FloatRegisters::f8, FloatRegister::Double };
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static constexpr FloatRegister f10 = { FloatRegisters::f10, FloatRegister::Double };
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static constexpr FloatRegister f12 = { FloatRegisters::f12, FloatRegister::Double };
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static constexpr FloatRegister f14 = { FloatRegisters::f14, FloatRegister::Double };
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static constexpr FloatRegister f16 = { FloatRegisters::f16, FloatRegister::Double };
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static constexpr FloatRegister f18 = { FloatRegisters::f18, FloatRegister::Double };
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static constexpr FloatRegister f20 = { FloatRegisters::f20, FloatRegister::Double };
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static constexpr FloatRegister f22 = { FloatRegisters::f22, FloatRegister::Double };
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static constexpr FloatRegister f24 = { FloatRegisters::f24, FloatRegister::Double };
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static constexpr FloatRegister f26 = { FloatRegisters::f26, FloatRegister::Double };
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static constexpr FloatRegister f28 = { FloatRegisters::f28, FloatRegister::Double };
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static constexpr FloatRegister f30 = { FloatRegisters::f30, FloatRegister::Double };
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// MIPS CPUs can only load multibyte data that is "naturally"
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// four-byte-aligned, sp register should be eight-byte-aligned.
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static constexpr uint32_t ABIStackAlignment = 8;
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static constexpr uint32_t JitStackAlignment = 8;
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static constexpr uint32_t JitStackValueAlignment = JitStackAlignment / sizeof(Value);
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static_assert(JitStackAlignment % sizeof(Value) == 0 && JitStackValueAlignment >= 1,
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"Stack alignment should be a non-zero multiple of sizeof(Value)");
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// TODO this is just a filler to prevent a build failure. The MIPS SIMD
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// alignment requirements still need to be explored.
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// TODO Copy the static_asserts from x64/x86 assembler files.
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static constexpr uint32_t SimdMemoryAlignment = 8;
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static constexpr uint32_t WasmStackAlignment = SimdMemoryAlignment;
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// Does this architecture support SIMD conversions between Uint32x4 and Float32x4?
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static constexpr bool SupportsUint32x4FloatConversions = false;
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// Does this architecture support comparisons of unsigned integer vectors?
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static constexpr bool SupportsUint8x16Compares = false;
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static constexpr bool SupportsUint16x8Compares = false;
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static constexpr bool SupportsUint32x4Compares = false;
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static constexpr Scale ScalePointer = TimesFour;
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class Assembler : public AssemblerMIPSShared
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{
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public:
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Assembler()
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: AssemblerMIPSShared()
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{ }
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static Condition UnsignedCondition(Condition cond);
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static Condition ConditionWithoutEqual(Condition cond);
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// MacroAssemblers hold onto gcthings, so they are traced by the GC.
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void trace(JSTracer* trc);
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static uintptr_t GetPointer(uint8_t*);
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protected:
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// This is used to access the odd register form the pair of single
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// precision registers that make one double register.
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FloatRegister getOddPair(FloatRegister reg) {
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MOZ_ASSERT(reg.isDouble());
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return reg.singleOverlay(1);
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}
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public:
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void Bind(uint8_t* rawCode, CodeOffset* label, const void* address);
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static void TraceJumpRelocations(JSTracer* trc, JitCode* code, CompactBufferReader& reader);
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static void TraceDataRelocations(JSTracer* trc, JitCode* code, CompactBufferReader& reader);
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static uint32_t InstructionImmediateSize() {
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return 2 * sizeof(uint32_t);
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}
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static uint32_t ExtractLuiOriValue(Instruction* inst0, Instruction* inst1);
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static void PatchDataWithValueCheck(CodeLocationLabel label, ImmPtr newValue,
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ImmPtr expectedValue);
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static void PatchDataWithValueCheck(CodeLocationLabel label, PatchedImmPtr newValue,
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PatchedImmPtr expectedValue);
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static void PatchInstructionImmediate(uint8_t* code, PatchedImmPtr imm);
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static uint32_t ExtractInstructionImmediate(uint8_t* code);
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static void ToggleCall(CodeLocationLabel inst_, bool enabled);
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}; // Assembler
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static const uint32_t NumIntArgRegs = 4;
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static inline bool
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GetIntArgReg(uint32_t usedArgSlots, Register* out)
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{
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if (usedArgSlots < NumIntArgRegs) {
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*out = Register::FromCode(a0.code() + usedArgSlots);
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return true;
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}
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return false;
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}
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// Get a register in which we plan to put a quantity that will be used as an
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// integer argument. This differs from GetIntArgReg in that if we have no more
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// actual argument registers to use we will fall back on using whatever
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// CallTempReg* don't overlap the argument registers, and only fail once those
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// run out too.
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static inline bool
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GetTempRegForIntArg(uint32_t usedIntArgs, uint32_t usedFloatArgs, Register* out)
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{
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// NOTE: We can't properly determine which regs are used if there are
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// float arguments. If this is needed, we will have to guess.
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MOZ_ASSERT(usedFloatArgs == 0);
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if (GetIntArgReg(usedIntArgs, out))
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return true;
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// Unfortunately, we have to assume things about the point at which
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// GetIntArgReg returns false, because we need to know how many registers it
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// can allocate.
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usedIntArgs -= NumIntArgRegs;
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if (usedIntArgs >= NumCallTempNonArgRegs)
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return false;
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*out = CallTempNonArgRegs[usedIntArgs];
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return true;
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}
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static inline uint32_t
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GetArgStackDisp(uint32_t usedArgSlots)
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{
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MOZ_ASSERT(usedArgSlots >= NumIntArgRegs);
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// Even register arguments have place reserved on stack.
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return usedArgSlots * sizeof(intptr_t);
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}
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} // namespace jit
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} // namespace js
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#endif /* jit_mips32_Assembler_mips32_h */
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