520 lines
18 KiB
C++
520 lines
18 KiB
C++
/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*- */
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// Copyright 2012 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef jit_arm_Simulator_arm_h
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#define jit_arm_Simulator_arm_h
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#ifdef JS_SIMULATOR_ARM
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#include "jit/arm/Architecture-arm.h"
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#include "jit/arm/disasm/Disasm-arm.h"
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#include "jit/IonTypes.h"
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#include "threading/Thread.h"
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#include "vm/MutexIDs.h"
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namespace js {
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namespace jit {
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class Simulator;
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class Redirection;
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class CachePage;
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class AutoLockSimulator;
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// When the SingleStepCallback is called, the simulator is about to execute
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// sim->get_pc() and the current machine state represents the completed
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// execution of the previous pc.
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typedef void (*SingleStepCallback)(void* arg, Simulator* sim, void* pc);
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// VFP rounding modes. See ARM DDI 0406B Page A2-29.
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enum VFPRoundingMode {
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SimRN = 0 << 22, // Round to Nearest.
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SimRP = 1 << 22, // Round towards Plus Infinity.
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SimRM = 2 << 22, // Round towards Minus Infinity.
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SimRZ = 3 << 22, // Round towards zero.
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// Aliases.
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kRoundToNearest = SimRN,
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kRoundToPlusInf = SimRP,
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kRoundToMinusInf = SimRM,
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kRoundToZero = SimRZ
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};
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const uint32_t kVFPRoundingModeMask = 3 << 22;
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typedef int32_t Instr;
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class SimInstruction;
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class Simulator
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{
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friend class Redirection;
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friend class AutoLockSimulatorCache;
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public:
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friend class ArmDebugger;
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enum Register {
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no_reg = -1,
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r0 = 0, r1, r2, r3, r4, r5, r6, r7,
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r8, r9, r10, r11, r12, r13, r14, r15,
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num_registers,
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sp = 13,
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lr = 14,
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pc = 15,
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s0 = 0, s1, s2, s3, s4, s5, s6, s7,
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s8, s9, s10, s11, s12, s13, s14, s15,
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s16, s17, s18, s19, s20, s21, s22, s23,
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s24, s25, s26, s27, s28, s29, s30, s31,
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num_s_registers = 32,
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d0 = 0, d1, d2, d3, d4, d5, d6, d7,
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d8, d9, d10, d11, d12, d13, d14, d15,
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d16, d17, d18, d19, d20, d21, d22, d23,
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d24, d25, d26, d27, d28, d29, d30, d31,
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num_d_registers = 32,
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q0 = 0, q1, q2, q3, q4, q5, q6, q7,
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q8, q9, q10, q11, q12, q13, q14, q15,
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num_q_registers = 16
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};
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// Returns nullptr on OOM.
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static Simulator* Create(JSContext* cx);
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static void Destroy(Simulator* simulator);
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// Constructor/destructor are for internal use only; use the static methods above.
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explicit Simulator(JSContext* cx);
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~Simulator();
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// The currently executing Simulator instance. Potentially there can be one
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// for each native thread.
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static Simulator* Current();
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static inline uintptr_t StackLimit() {
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return Simulator::Current()->stackLimit();
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}
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// Disassemble some instructions starting at instr and print them
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// on stdout. Useful for working within GDB after a MOZ_CRASH(),
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// among other things.
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//
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// Typical use within a crashed instruction decoding method is simply:
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//
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// call Simulator::disassemble(instr, 1)
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//
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// or use one of the more convenient inline methods below.
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static void disassemble(SimInstruction* instr, size_t n);
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// Disassemble one instruction.
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// "call disasm(instr)"
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void disasm(SimInstruction* instr);
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// Disassemble n instructions starting at instr.
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// "call disasm(instr, 3)"
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void disasm(SimInstruction* instr, size_t n);
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// Skip backwards m instructions before starting, then disassemble n instructions.
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// "call disasm(instr, 3, 7)"
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void disasm(SimInstruction* instr, size_t m, size_t n);
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uintptr_t* addressOfStackLimit();
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// Accessors for register state. Reading the pc value adheres to the ARM
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// architecture specification and is off by a 8 from the currently executing
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// instruction.
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void set_register(int reg, int32_t value);
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int32_t get_register(int reg) const;
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double get_double_from_register_pair(int reg);
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void set_register_pair_from_double(int reg, double* value);
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void set_dw_register(int dreg, const int* dbl);
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// Support for VFP.
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void get_d_register(int dreg, uint64_t* value);
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void set_d_register(int dreg, const uint64_t* value);
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void get_d_register(int dreg, uint32_t* value);
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void set_d_register(int dreg, const uint32_t* value);
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void get_q_register(int qreg, uint64_t* value);
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void set_q_register(int qreg, const uint64_t* value);
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void get_q_register(int qreg, uint32_t* value);
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void set_q_register(int qreg, const uint32_t* value);
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void set_s_register(int reg, unsigned int value);
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unsigned int get_s_register(int reg) const;
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void set_d_register_from_double(int dreg, const double& dbl) {
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setVFPRegister<double, 2>(dreg, dbl);
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}
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void get_double_from_d_register(int dreg, double* out) {
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getFromVFPRegister<double, 2>(dreg, out);
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}
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void set_s_register_from_float(int sreg, const float flt) {
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setVFPRegister<float, 1>(sreg, flt);
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}
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void get_float_from_s_register(int sreg, float* out) {
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getFromVFPRegister<float, 1>(sreg, out);
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}
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void set_s_register_from_sinteger(int sreg, const int sint) {
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setVFPRegister<int, 1>(sreg, sint);
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}
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int get_sinteger_from_s_register(int sreg) {
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int ret;
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getFromVFPRegister<int, 1>(sreg, &ret);
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return ret;
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}
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// Special case of set_register and get_register to access the raw PC value.
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void set_pc(int32_t value);
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int32_t get_pc() const;
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template <typename T>
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T get_pc_as() const { return reinterpret_cast<T>(get_pc()); }
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void set_resume_pc(void* value) {
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resume_pc_ = int32_t(value);
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}
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void enable_single_stepping(SingleStepCallback cb, void* arg);
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void disable_single_stepping();
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uintptr_t stackLimit() const;
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bool overRecursed(uintptr_t newsp = 0) const;
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bool overRecursedWithExtra(uint32_t extra) const;
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// Executes ARM instructions until the PC reaches end_sim_pc.
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template<bool EnableStopSimAt>
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void execute();
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// Sets up the simulator state and grabs the result on return.
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int32_t call(uint8_t* entry, int argument_count, ...);
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// Debugger input.
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void setLastDebuggerInput(char* input);
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char* lastDebuggerInput() { return lastDebuggerInput_; }
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// Returns true if pc register contains one of the 'special_values' defined
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// below (bad_lr, end_sim_pc).
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bool has_bad_pc() const;
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private:
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enum special_values {
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// Known bad pc value to ensure that the simulator does not execute
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// without being properly setup.
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bad_lr = -1,
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// A pc value used to signal the simulator to stop execution. Generally
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// the lr is set to this value on transition from native C code to
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// simulated execution, so that the simulator can "return" to the native
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// C code.
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end_sim_pc = -2
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};
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// ForbidUnaligned means "always fault on unaligned access".
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//
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// AllowUnaligned means "allow the unaligned access if other conditions are
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// met". The "other conditions" vary with the instruction: For all
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// instructions the base condition is !HasAlignmentFault(), ie, the chip is
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// configured to allow unaligned accesses. For instructions like VLD1
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// there is an additional constraint that the alignment attribute in the
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// instruction must be set to "default alignment".
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enum UnalignedPolicy {
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ForbidUnaligned,
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AllowUnaligned
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};
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bool init();
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// Checks if the current instruction should be executed based on its
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// condition bits.
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inline bool conditionallyExecute(SimInstruction* instr);
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// Helper functions to set the conditional flags in the architecture state.
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void setNZFlags(int32_t val);
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void setCFlag(bool val);
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void setVFlag(bool val);
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bool carryFrom(int32_t left, int32_t right, int32_t carry = 0);
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bool borrowFrom(int32_t left, int32_t right);
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bool overflowFrom(int32_t alu_out, int32_t left, int32_t right, bool addition);
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inline int getCarry() { return c_flag_ ? 1 : 0; };
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// Support for VFP.
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void compute_FPSCR_Flags(double val1, double val2);
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void copy_FPSCR_to_APSR();
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inline void canonicalizeNaN(double* value);
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inline void canonicalizeNaN(float* value);
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// Helper functions to decode common "addressing" modes
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int32_t getShiftRm(SimInstruction* instr, bool* carry_out);
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int32_t getImm(SimInstruction* instr, bool* carry_out);
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int32_t processPU(SimInstruction* instr, int num_regs, int operand_size,
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intptr_t* start_address, intptr_t* end_address);
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void handleRList(SimInstruction* instr, bool load);
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void handleVList(SimInstruction* inst);
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void softwareInterrupt(SimInstruction* instr);
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// Stop helper functions.
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inline bool isStopInstruction(SimInstruction* instr);
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inline bool isWatchedStop(uint32_t bkpt_code);
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inline bool isEnabledStop(uint32_t bkpt_code);
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inline void enableStop(uint32_t bkpt_code);
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inline void disableStop(uint32_t bkpt_code);
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inline void increaseStopCounter(uint32_t bkpt_code);
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void printStopInfo(uint32_t code);
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// Handle any wasm faults, returning true if the fault was handled.
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inline bool handleWasmFault(int32_t addr, unsigned numBytes);
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// Read and write memory.
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inline uint8_t readBU(int32_t addr);
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inline int8_t readB(int32_t addr);
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inline void writeB(int32_t addr, uint8_t value);
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inline void writeB(int32_t addr, int8_t value);
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inline uint8_t readExBU(int32_t addr);
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inline int32_t writeExB(int32_t addr, uint8_t value);
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inline uint16_t readHU(int32_t addr, SimInstruction* instr);
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inline int16_t readH(int32_t addr, SimInstruction* instr);
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// Note: Overloaded on the sign of the value.
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inline void writeH(int32_t addr, uint16_t value, SimInstruction* instr);
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inline void writeH(int32_t addr, int16_t value, SimInstruction* instr);
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inline uint16_t readExHU(int32_t addr, SimInstruction* instr);
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inline int32_t writeExH(int32_t addr, uint16_t value, SimInstruction* instr);
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inline int readW(int32_t addr, SimInstruction* instr, UnalignedPolicy f = ForbidUnaligned);
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inline void writeW(int32_t addr, int value, SimInstruction* instr, UnalignedPolicy f = ForbidUnaligned);
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inline uint64_t readQ(int32_t addr, SimInstruction* instr, UnalignedPolicy f = ForbidUnaligned);
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inline void writeQ(int32_t addr, uint64_t value, SimInstruction* instr, UnalignedPolicy f = ForbidUnaligned);
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inline int readExW(int32_t addr, SimInstruction* instr);
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inline int writeExW(int32_t addr, int value, SimInstruction* instr);
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int32_t* readDW(int32_t addr);
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void writeDW(int32_t addr, int32_t value1, int32_t value2);
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int32_t readExDW(int32_t addr, int32_t* hibits);
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int32_t writeExDW(int32_t addr, int32_t value1, int32_t value2);
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// Executing is handled based on the instruction type.
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// Both type 0 and type 1 rolled into one.
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void decodeType01(SimInstruction* instr);
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void decodeType2(SimInstruction* instr);
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void decodeType3(SimInstruction* instr);
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void decodeType4(SimInstruction* instr);
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void decodeType5(SimInstruction* instr);
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void decodeType6(SimInstruction* instr);
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void decodeType7(SimInstruction* instr);
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// Support for VFP.
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void decodeTypeVFP(SimInstruction* instr);
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void decodeType6CoprocessorIns(SimInstruction* instr);
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void decodeSpecialCondition(SimInstruction* instr);
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void decodeVMOVBetweenCoreAndSinglePrecisionRegisters(SimInstruction* instr);
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void decodeVCMP(SimInstruction* instr);
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void decodeVCVTBetweenDoubleAndSingle(SimInstruction* instr);
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void decodeVCVTBetweenFloatingPointAndInteger(SimInstruction* instr);
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void decodeVCVTBetweenFloatingPointAndIntegerFrac(SimInstruction* instr);
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// Support for some system functions.
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void decodeType7CoprocessorIns(SimInstruction* instr);
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// Executes one instruction.
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void instructionDecode(SimInstruction* instr);
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public:
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static bool ICacheCheckingEnabled;
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static void FlushICache(void* start, size_t size);
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static int64_t StopSimAt;
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// For testing the MoveResolver code, a MoveResolver is set up, and
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// the VFP registers are loaded with pre-determined values,
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// then the sequence of code is simulated. In order to test this with the
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// simulator, the callee-saved registers can't be trashed. This flag
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// disables that feature.
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bool skipCalleeSavedRegsCheck;
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// Runtime call support.
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static void* RedirectNativeFunction(void* nativeFunction, ABIFunctionType type);
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private:
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// Handle arguments and return value for runtime FP functions.
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void getFpArgs(double* x, double* y, int32_t* z);
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void getFpFromStack(int32_t* stack, double* x1);
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void setCallResultDouble(double result);
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void setCallResultFloat(float result);
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void setCallResult(int64_t res);
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void scratchVolatileRegisters(bool scratchFloat = true);
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template<class ReturnType, int register_size>
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void getFromVFPRegister(int reg_index, ReturnType* out);
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template<class InputType, int register_size>
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void setVFPRegister(int reg_index, const InputType& value);
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void callInternal(uint8_t* entry);
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JSContext* const cx_;
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// Architecture state.
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// Saturating instructions require a Q flag to indicate saturation.
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// There is currently no way to read the CPSR directly, and thus read the Q
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// flag, so this is left unimplemented.
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int32_t registers_[16];
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bool n_flag_;
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bool z_flag_;
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bool c_flag_;
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bool v_flag_;
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// VFP architecture state.
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uint32_t vfp_registers_[num_d_registers * 2];
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bool n_flag_FPSCR_;
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bool z_flag_FPSCR_;
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bool c_flag_FPSCR_;
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bool v_flag_FPSCR_;
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// VFP rounding mode. See ARM DDI 0406B Page A2-29.
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VFPRoundingMode FPSCR_rounding_mode_;
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bool FPSCR_default_NaN_mode_;
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// VFP FP exception flags architecture state.
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bool inv_op_vfp_flag_;
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bool div_zero_vfp_flag_;
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bool overflow_vfp_flag_;
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bool underflow_vfp_flag_;
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bool inexact_vfp_flag_;
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// Simulator support.
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char* stack_;
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uintptr_t stackLimit_;
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bool pc_modified_;
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int64_t icount_;
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int32_t resume_pc_;
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// Debugger input.
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char* lastDebuggerInput_;
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// Registered breakpoints.
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SimInstruction* break_pc_;
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Instr break_instr_;
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// Single-stepping support
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bool single_stepping_;
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SingleStepCallback single_step_callback_;
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void* single_step_callback_arg_;
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// A stop is watched if its code is less than kNumOfWatchedStops.
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// Only watched stops support enabling/disabling and the counter feature.
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static const uint32_t kNumOfWatchedStops = 256;
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// Breakpoint is disabled if bit 31 is set.
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static const uint32_t kStopDisabledBit = 1 << 31;
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// A stop is enabled, meaning the simulator will stop when meeting the
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// instruction, if bit 31 of watched_stops_[code].count is unset.
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// The value watched_stops_[code].count & ~(1 << 31) indicates how many times
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// the breakpoint was hit or gone through.
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struct StopCountAndDesc {
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uint32_t count;
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char* desc;
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};
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StopCountAndDesc watched_stops_[kNumOfWatchedStops];
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public:
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int64_t icount() {
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return icount_;
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}
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private:
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// ICache checking.
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struct ICacheHasher {
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typedef void* Key;
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typedef void* Lookup;
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static HashNumber hash(const Lookup& l);
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static bool match(const Key& k, const Lookup& l);
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};
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public:
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typedef HashMap<void*, CachePage*, ICacheHasher, SystemAllocPolicy> ICacheMap;
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private:
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// This lock creates a critical section around 'redirection_' and
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// 'icache_', which are referenced both by the execution engine
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// and by the off-thread compiler (see Redirection::Get in the cpp file).
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Mutex cacheLock_;
|
|
#ifdef DEBUG
|
|
mozilla::Maybe<Thread::Id> cacheLockHolder_;
|
|
#endif
|
|
|
|
Redirection* redirection_;
|
|
ICacheMap icache_;
|
|
|
|
public:
|
|
ICacheMap& icache() {
|
|
// Technically we need the lock to access the innards of the
|
|
// icache, not to take its address, but the latter condition
|
|
// serves as a useful complement to the former.
|
|
MOZ_ASSERT(cacheLockHolder_.isSome());
|
|
return icache_;
|
|
}
|
|
|
|
Redirection* redirection() const {
|
|
MOZ_ASSERT(cacheLockHolder_.isSome());
|
|
return redirection_;
|
|
}
|
|
|
|
void setRedirection(js::jit::Redirection* redirection) {
|
|
MOZ_ASSERT(cacheLockHolder_.isSome());
|
|
redirection_ = redirection;
|
|
}
|
|
|
|
private:
|
|
// Exclusive access monitor
|
|
void exclusiveMonitorSet(uint64_t value);
|
|
uint64_t exclusiveMonitorGetAndClear(bool* held);
|
|
void exclusiveMonitorClear();
|
|
|
|
bool exclusiveMonitorHeld_;
|
|
uint64_t exclusiveMonitor_;
|
|
};
|
|
|
|
#define JS_CHECK_SIMULATOR_RECURSION_WITH_EXTRA(cx, extra, onerror) \
|
|
JS_BEGIN_MACRO \
|
|
if (cx->runtime()->simulator()->overRecursedWithExtra(extra)) { \
|
|
js::ReportOverRecursed(cx); \
|
|
onerror; \
|
|
} \
|
|
JS_END_MACRO
|
|
|
|
} // namespace jit
|
|
} // namespace js
|
|
|
|
#endif /* JS_SIMULATOR_ARM */
|
|
|
|
#endif /* jit_arm_Simulator_arm_h */
|