348 lines
6.2 KiB
C
348 lines
6.2 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "ureg.h"
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#include "../port/pci.h"
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#include "../port/error.h"
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/* this driver doesn't implement the management interrupts. we
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* leave the LM78 interrupts set to whatever the BIOS did. we do
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* allow reading and writing the the readouts and alarm values.
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* Read(2)ing or write(2)ing at offset 0x0-0x1f, is
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* equivalent to reading or writing lm78 registers 0x20-0x3f.
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*/
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enum
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{
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/* address of chip on serial interface */
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Serialaddr= 0x2d,
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/* parallel access registers */
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Rpaddr= 0x5,
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Bbusy= (1<<7),
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Rpdata= 0x6,
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/* internal register addresses */
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Rconfig= 0x40,
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Bstart= (1<<0),
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Bsmiena= (1<<1),
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Birqena= (1<<2),
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Bintclr= (1<<3),
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Breset= (1<<4),
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Bnmi= (1<<5), /* if set, use nmi, else irq */
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Bpowbypass= (1<<6),
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Binit= (1<<7),
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Ristat1= 0x41,
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Ristat2= 0x42,
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Rsmimask1= 0x43,
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Rsmimask2= 0x44,
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Rnmimask1= 0x45,
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Rnmimask2= 0x46,
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Rvidfan= 0x47, /* set fan counter, and read voltage level */
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Mvid= 0x0f,
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Mfan= 0xf0,
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Raddr= 0x48, /* address used on serial bus */
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Rresetid= 0x49, /* chip reset and ID register */
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Rpost= 0x00, /* start of post ram */
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Rvalue= 0x20, /* start of value ram */
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VRsize= 0x20, /* size of value ram */
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};
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enum
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{
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Qdir,
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Qlm78vram,
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};
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static Dirtab lm78dir[] = {
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".", { Qdir, 0, QTDIR}, 0, 0555,
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"lm78vram", { Qlm78vram, 0 }, 0, 0444,
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};
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/* interface type */
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enum
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{
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None= 0,
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Smbus,
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Parallel,
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};
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static struct {
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QLock;
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int probed;
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int ifc; /* which interface is connected */
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SMBus *smbus; /* serial interface */
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int port; /* parallel interface */
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} lm78;
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extern SMBus* piix4smbus(void);
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/* wait for device to become quiescent and then set the */
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/* register address */
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static void
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setreg(int reg)
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{
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int tries;
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for(tries = 0; tries < 1000000; tries++)
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if((inb(lm78.port+Rpaddr) & Bbusy) == 0){
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outb(lm78.port+Rpaddr, reg);
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return;
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}
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error("lm78 broken");
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}
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/* routines that actually touch the device */
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static void
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lm78wrreg(int reg, uchar val)
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{
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if(waserror()){
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qunlock(&lm78);
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nexterror();
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}
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qlock(&lm78);
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switch(lm78.ifc){
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case Smbus:
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lm78.smbus->transact(lm78.smbus, SMBbytewrite, Serialaddr, reg, &val);
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break;
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case Parallel:
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setreg(reg);
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outb(lm78.port+Rpdata, val);
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break;
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default:
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error(Enodev);
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break;
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}
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qunlock(&lm78);
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poperror();
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}
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static int
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lm78rdreg(int reg)
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{
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uchar val;
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if(waserror()){
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qunlock(&lm78);
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nexterror();
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}
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qlock(&lm78);
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switch(lm78.ifc){
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case Smbus:
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lm78.smbus->transact(lm78.smbus, SMBsend, Serialaddr, reg, nil);
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lm78.smbus->transact(lm78.smbus, SMBrecv, Serialaddr, 0, &val);
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break;
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case Parallel:
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setreg(reg);
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val = inb(lm78.port+Rpdata);
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break;
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default:
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error(Enodev);
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break;
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}
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qunlock(&lm78);
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poperror();
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return val;
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}
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/* start the chip monitoring but don't change any smi
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* interrupts and/or alarms that the BIOS may have set up.
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* this isn't locked because it's thought to be idempotent
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*/
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static void
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lm78enable(void)
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{
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uchar config;
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if(lm78.ifc == None)
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error(Enodev);
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if(lm78.probed == 0){
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/* make sure its really there */
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if(lm78rdreg(Raddr) != Serialaddr){
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lm78.ifc = None;
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error(Enodev);
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} else {
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/* start the sampling */
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config = lm78rdreg(Rconfig);
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config = (config | Bstart) & ~(Bintclr|Binit);
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lm78wrreg(Rconfig, config);
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pprint("Rvidfan %2.2ux\n", lm78rdreg(Rconfig), lm78rdreg(Rvidfan));
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}
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lm78.probed = 1;
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}
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}
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enum
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{
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IntelVendID= 0x8086,
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PiixID= 0x122E,
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Piix3ID= 0x7000,
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Piix4PMID= 0x7113, /* PIIX4 power management function */
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PCSC= 0x78, /* programmable chip select control register */
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PCSC8bytes= 0x01,
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};
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/* figure out what kind of interface we could have */
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void
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lm78reset(void)
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{
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int pcs;
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Pcidev *p;
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lm78.ifc = None;
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p = nil;
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while((p = pcimatch(p, IntelVendID, 0)) != nil){
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switch(p->did){
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/* these bridges use the PCSC to map the lm78 into port space. */
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/* for this case the lm78's CS# select is connected to the PIIX's */
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/* PCS# output and the bottom 3 bits of address are passed to the */
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/* LM78's A0-A2 inputs. */
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case PiixID:
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case Piix3ID:
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pcs = pcicfgr16(p, PCSC);
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if(pcs & 3) {
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/* already enabled */
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lm78.port = pcs & ~3;
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lm78.ifc = Parallel;
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return;
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}
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/* enable the chip, use default address 0x50 */
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pcicfgw16(p, PCSC, 0x50|PCSC8bytes);
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pcs = pcicfgr16(p, PCSC);
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lm78.port = pcs & ~3;
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lm78.ifc = Parallel;
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return;
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/* this bridge puts the lm78's serial interface on the smbus */
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case Piix4PMID:
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lm78.smbus = piix4smbus();
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if(lm78.smbus == nil)
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continue;
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print("found piix4 smbus, base %lud\n", lm78.smbus->base);
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lm78.ifc = Smbus;
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return;
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}
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}
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}
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Walkqid *
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lm78walk(Chan* c, Chan *nc, char** name, int nname)
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{
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return devwalk(c, nc, name, nname, lm78dir, nelem(lm78dir), devgen);
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}
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static int
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lm78stat(Chan* c, uchar* dp, int n)
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{
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return devstat(c, dp, n, lm78dir, nelem(lm78dir), devgen);
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}
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static Chan*
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lm78open(Chan* c, int omode)
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{
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return devopen(c, omode, lm78dir, nelem(lm78dir), devgen);
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}
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static void
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lm78close(Chan*)
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{
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}
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enum
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{
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Linelen= 25,
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};
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static long
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lm78read(Chan *c, void *a, long n, vlong offset)
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{
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uchar *va = a;
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int off, e;
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off = offset;
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switch((ulong)c->qid.path){
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case Qdir:
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return devdirread(c, a, n, lm78dir, nelem(lm78dir), devgen);
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case Qlm78vram:
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if(off >= VRsize)
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return 0;
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e = off + n;
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if(e > VRsize)
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e = VRsize;
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for(; off < e; off++)
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*va++ = lm78rdreg(Rvalue+off);
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return (int)(va - (uchar*)a);
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}
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return 0;
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}
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static long
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lm78write(Chan *c, void *a, long n, vlong offset)
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{
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uchar *va = a;
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int off, e;
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off = offset;
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switch((ulong)c->qid.path){
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default:
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error(Eperm);
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case Qlm78vram:
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if(off >= VRsize)
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return 0;
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e = off + n;
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if(e > VRsize)
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e = VRsize;
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for(; off < e; off++)
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lm78wrreg(Rvalue+off, *va++);
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return va - (uchar*)a;
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}
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return 0;
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}
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extern Dev lm78devtab;
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static Chan*
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lm78attach(char* spec)
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{
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lm78enable();
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return devattach(lm78devtab.dc, spec);
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}
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Dev lm78devtab = {
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'T',
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"lm78",
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lm78reset,
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devinit,
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devshutdown,
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lm78attach,
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lm78walk,
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lm78stat,
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lm78open,
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devcreate,
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lm78close,
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lm78read,
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devbread,
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lm78write,
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devbwrite,
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devremove,
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devwstat,
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};
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