773 lines
15 KiB
C
773 lines
15 KiB
C
/*
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* this doesn't attempt to implement ARM floating-point properties
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* that aren't visible in the Inferno environment.
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* all arithmetic is done in double precision.
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* the FP trap status isn't updated.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "ureg.h"
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#include "arm.h"
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#include "fpi.h"
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/* undef this if correct kernel r13 isn't in Ureg;
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* check calculation in fpiarm below
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*/
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#define REG(ur, x) (*(long*)(((char*)(ur))+roff[(x)]))
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#define FR(ufp, x) (*(Internal*)(ufp)->regs[(x)&(Nfpctlregs - 1)])
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typedef struct FP2 FP2;
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typedef struct FP1 FP1;
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struct FP2 {
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char* name;
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void (*f)(Internal, Internal, Internal*);
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};
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struct FP1 {
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char* name;
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void (*f)(Internal*, Internal*);
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};
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enum {
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N = 1<<31,
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Z = 1<<30,
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C = 1<<29,
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V = 1<<28,
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REGPC = 15,
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};
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enum {
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fpemudebug = 0,
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};
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#undef OFR
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#define OFR(X) ((ulong)&((Ureg*)0)->X)
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static int roff[] = {
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OFR(r0), OFR(r1), OFR(r2), OFR(r3),
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OFR(r4), OFR(r5), OFR(r6), OFR(r7),
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OFR(r8), OFR(r9), OFR(r10), OFR(r11),
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OFR(r12), OFR(r13), OFR(r14), OFR(pc),
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};
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static Internal fpconst[8] = { /* indexed by op&7 (ARM 7500 FPA) */
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/* s, e, l, h */
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{0, 0x1, 0x00000000, 0x00000000}, /* 0.0 */
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{0, 0x3FF, 0x00000000, 0x08000000}, /* 1.0 */
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{0, 0x400, 0x00000000, 0x08000000}, /* 2.0 */
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{0, 0x400, 0x00000000, 0x0C000000}, /* 3.0 */
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{0, 0x401, 0x00000000, 0x08000000}, /* 4.0 */
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{0, 0x401, 0x00000000, 0x0A000000}, /* 5.0 */
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{0, 0x3FE, 0x00000000, 0x08000000}, /* 0.5 */
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{0, 0x402, 0x00000000, 0x0A000000}, /* 10.0 */
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};
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/*
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* arm binary operations
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*/
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static void
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fadd(Internal m, Internal n, Internal *d)
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{
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(m.s == n.s? fpiadd: fpisub)(&m, &n, d);
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}
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static void
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fsub(Internal m, Internal n, Internal *d)
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{
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m.s ^= 1;
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(m.s == n.s? fpiadd: fpisub)(&m, &n, d);
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}
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static void
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fsubr(Internal m, Internal n, Internal *d)
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{
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n.s ^= 1;
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(n.s == m.s? fpiadd: fpisub)(&n, &m, d);
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}
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static void
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fmul(Internal m, Internal n, Internal *d)
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{
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fpimul(&m, &n, d);
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}
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static void
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fdiv(Internal m, Internal n, Internal *d)
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{
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fpidiv(&m, &n, d);
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}
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static void
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fdivr(Internal m, Internal n, Internal *d)
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{
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fpidiv(&n, &m, d);
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}
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/*
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* arm unary operations
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*/
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static void
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fmov(Internal *m, Internal *d)
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{
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*d = *m;
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}
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static void
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fmovn(Internal *m, Internal *d)
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{
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*d = *m;
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d->s ^= 1;
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}
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static void
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fabsf(Internal *m, Internal *d)
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{
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*d = *m;
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d->s = 0;
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}
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static void
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frnd(Internal *m, Internal *d)
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{
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short e;
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(m->s? fsub: fadd)(fpconst[6], *m, d);
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if(IsWeird(d))
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return;
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fpiround(d);
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e = (d->e - ExpBias) + 1;
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if(e <= 0)
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SetZero(d);
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else if(e > FractBits){
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if(e < 2*FractBits)
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d->l &= ~((1<<(2*FractBits - e))-1);
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}else{
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d->l = 0;
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if(e < FractBits)
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d->h &= ~((1<<(FractBits-e))-1);
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}
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}
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/*
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* ARM 7500 FPA opcodes
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*/
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static FP1 optab1[16] = { /* Fd := OP Fm */
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[0] {"MOVF", fmov},
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[1] {"NEGF", fmovn},
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[2] {"ABSF", fabsf},
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[3] {"RNDF", frnd},
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[4] {"SQTF", /*fsqt*/0},
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/* LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN all `deprecated' */
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/* URD and NRM aren't implemented */
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};
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static FP2 optab2[16] = { /* Fd := Fn OP Fm */
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[0] {"ADDF", fadd},
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[1] {"MULF", fmul},
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[2] {"SUBF", fsub},
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[3] {"RSUBF", fsubr},
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[4] {"DIVF", fdiv},
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[5] {"RDIVF", fdivr},
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/* POW, RPW deprecated */
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[8] {"REMF", /*frem*/0},
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[9] {"FMF", fmul}, /* fast multiply */
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[10] {"FDV", fdiv}, /* fast divide */
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[11] {"FRD", fdivr}, /* fast reverse divide */
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/* POL deprecated */
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};
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/*
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* ARM VFP opcodes
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*/
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static FP1 voptab1[32] = { /* Vd := OP Vm */
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[0] {"MOVF", fmov},
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[1] {"ABSF", fabsf},
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[2] {"NEGF", fmovn},
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[15] {"CVTF", fmov},
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};
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static FP2 voptab2[16] = { /* Vd := Vn FOP Fm */
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[4] {"MULF", fmul},
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[6] {"ADDF", fadd},
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[7] {"SUBF", fsub},
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[8] {"DIVF", fdiv},
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};
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static ulong
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fcmp(Internal *n, Internal *m)
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{
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int i;
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Internal rm, rn;
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if(IsWeird(m) || IsWeird(n)){
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/* BUG: should trap if not masked */
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return V|C;
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}
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rn = *n;
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rm = *m;
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fpiround(&rn);
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fpiround(&rm);
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i = fpicmp(&rn, &rm);
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if(i > 0)
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return C;
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else if(i == 0)
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return C|Z;
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else
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return N;
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}
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static void
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fld(void (*f)(Internal*, void*), int d, ulong ea, int n, FPsave *ufp)
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{
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void *mem;
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mem = (void*)ea;
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(*f)(&FR(ufp, d), mem);
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if(fpemudebug)
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print("MOV%c #%lux, F%d\n", n==8? 'D': 'F', ea, d);
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}
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static void
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fst(void (*f)(void*, Internal*), ulong ea, int s, int n, FPsave *ufp)
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{
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Internal tmp;
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void *mem;
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mem = (void*)ea;
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tmp = FR(ufp, s);
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if(fpemudebug)
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print("MOV%c F%d,#%lux\n", n==8? 'D': 'F', s, ea);
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(*f)(mem, &tmp);
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}
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static int
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condok(int cc, int c)
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{
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switch(c){
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case 0: /* Z set */
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return cc&Z;
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case 1: /* Z clear */
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return (cc&Z) == 0;
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case 2: /* C set */
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return cc&C;
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case 3: /* C clear */
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return (cc&C) == 0;
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case 4: /* N set */
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return cc&N;
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case 5: /* N clear */
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return (cc&N) == 0;
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case 6: /* V set */
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return cc&V;
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case 7: /* V clear */
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return (cc&V) == 0;
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case 8: /* C set and Z clear */
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return cc&C && (cc&Z) == 0;
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case 9: /* C clear or Z set */
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return (cc&C) == 0 || cc&Z;
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case 10: /* N set and V set, or N clear and V clear */
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return (~cc&(N|V))==0 || (cc&(N|V)) == 0;
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case 11: /* N set and V clear, or N clear and V set */
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return (cc&(N|V))==N || (cc&(N|V))==V;
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case 12: /* Z clear, and either N set and V set or N clear and V clear */
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return (cc&Z) == 0 && ((~cc&(N|V))==0 || (cc&(N|V))==0);
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case 13: /* Z set, or N set and V clear or N clear and V set */
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return (cc&Z) || (cc&(N|V))==N || (cc&(N|V))==V;
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case 14: /* always */
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return 1;
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case 15: /* never (reserved) */
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return 0;
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}
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return 0; /* not reached */
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}
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static void
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unimp(ulong pc, ulong op)
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{
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char buf[60];
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snprint(buf, sizeof(buf), "sys: fp: pc=%lux unimp fp 0x%.8lux", pc, op);
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if(fpemudebug)
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print("FPE: %s\n", buf);
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error(buf);
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/* no return */
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}
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static void
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fpaemu(ulong pc, ulong op, Ureg *ur, FPsave *ufp)
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{
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int rn, rd, tag, o;
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long off;
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ulong ea;
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Internal tmp, *fm, *fn;
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/* note: would update fault status here if we noted numeric exceptions */
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/*
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* LDF, STF; 10.1.1
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*/
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if(((op>>25)&7) == 6){
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if(op & (1<<22))
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unimp(pc, op); /* packed or extended */
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rn = (op>>16)&0xF;
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off = (op&0xFF)<<2;
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if((op & (1<<23)) == 0)
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off = -off;
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ea = REG(ur, rn);
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if(rn == REGPC)
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ea += 8;
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if(op & (1<<24))
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ea += off;
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rd = (op>>12)&7;
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if(op & (1<<20)){
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if(op & (1<<15))
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fld(fpid2i, rd, ea, 8, ufp);
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else
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fld(fpis2i, rd, ea, 4, ufp);
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}else{
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if(op & (1<<15))
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fst(fpii2d, ea, rd, 8, ufp);
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else
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fst(fpii2s, ea, rd, 4, ufp);
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}
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if((op & (1<<24)) == 0)
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ea += off;
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if(op & (1<<21))
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REG(ur, rn) = ea;
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return;
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}
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/*
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* CPRT/transfer, 10.3
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*/
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if(op & (1<<4)){
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rd = (op>>12) & 0xF;
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/*
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* compare, 10.3.1
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*/
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if(rd == 15 && op & (1<<20)){
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rn = (op>>16)&7;
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fn = &FR(ufp, rn);
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if(op & (1<<3)){
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fm = &fpconst[op&7];
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if(fpemudebug)
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tag = 'C';
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}else{
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fm = &FR(ufp, op&7);
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if(fpemudebug)
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tag = 'F';
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}
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switch((op>>21)&7){
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default:
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unimp(pc, op);
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case 4: /* CMF: Fn :: Fm */
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case 6: /* CMFE: Fn :: Fm (with exception) */
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ur->psr &= ~(N|C|Z|V);
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ur->psr |= fcmp(fn, fm);
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break;
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case 5: /* CNF: Fn :: -Fm */
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case 7: /* CNFE: Fn :: -Fm (with exception) */
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tmp = *fm;
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tmp.s ^= 1;
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ur->psr &= ~(N|C|Z|V);
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ur->psr |= fcmp(fn, &tmp);
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break;
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}
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if(fpemudebug)
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print("CMPF %c%d,F%ld =%#lux\n",
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tag, rn, op&7, ur->psr>>28);
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return;
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}
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/*
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* other transfer, 10.3
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*/
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switch((op>>20)&0xF){
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default:
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unimp(pc, op);
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case 0: /* FLT */
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rn = (op>>16) & 7;
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fpiw2i(&FR(ufp, rn), ®(ur, rd));
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if(fpemudebug)
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print("MOVW[FD] R%d, F%d\n", rd, rn);
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break;
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case 1: /* FIX */
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if(op & (1<<3))
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unimp(pc, op);
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rn = op & 7;
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tmp = FR(ufp, rn);
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fpii2w(®(ur, rd), &tmp);
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if(fpemudebug)
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print("MOV[FD]W F%d, R%d =%ld\n", rn, rd, REG(ur, rd));
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break;
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case 2: /* FPSR := Rd */
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ufp->status = REG(ur, rd);
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if(fpemudebug)
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print("MOVW R%d, FPSR\n", rd);
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break;
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case 3: /* Rd := FPSR */
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REG(ur, rd) = ufp->status;
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if(fpemudebug)
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print("MOVW FPSR, R%d\n", rd);
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break;
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case 4: /* FPCR := Rd */
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ufp->control = REG(ur, rd);
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if(fpemudebug)
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print("MOVW R%d, FPCR\n", rd);
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break;
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case 5: /* Rd := FPCR */
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REG(ur, rd) = ufp->control;
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if(fpemudebug)
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print("MOVW FPCR, R%d\n", rd);
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break;
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}
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return;
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}
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/*
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* arithmetic
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*/
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if(op & (1<<3)){ /* constant */
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fm = &fpconst[op&7];
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if(fpemudebug)
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tag = 'C';
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}else{
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fm = &FR(ufp, op&7);
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if(fpemudebug)
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tag = 'F';
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}
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rd = (op>>12)&7;
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o = (op>>20)&0xF;
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if(op & (1<<15)){ /* monadic */
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FP1 *fp;
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fp = &optab1[o];
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if(fp->f == nil)
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unimp(pc, op);
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if(fpemudebug)
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print("%s %c%ld,F%d\n", fp->name, tag, op&7, rd);
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(*fp->f)(fm, &FR(ufp, rd));
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} else {
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FP2 *fp;
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fp = &optab2[o];
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if(fp->f == nil)
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unimp(pc, op);
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rn = (op>>16)&7;
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if(fpemudebug)
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print("%s %c%ld,F%d,F%d\n", fp->name, tag, op&7, rn, rd);
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(*fp->f)(*fm, FR(ufp, rn), &FR(ufp, rd));
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}
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}
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static void
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vfpoptoi(Internal *fm, uchar o2, uchar o4)
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{
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fm->s = o2>>3;
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fm->e = ((o2>>3) | ~(o2 & 4)) - 3 + ExpBias;
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fm->l = 0;
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fm->h = o4 << (20+NGuardBits);
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if(fm->e)
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fm->h |= HiddenBit;
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else
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fm->e++;
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}
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static void
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vfpemu(ulong pc, ulong op, Ureg *ur, FPsave *ufp)
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{
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int sz, vd, o1, o2, o3, o4, o, tag;
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long off;
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ulong ea;
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Word w;
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Internal *fm, fc;
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/* note: would update fault status here if we noted numeric exceptions */
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sz = op & (1<<8);
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o1 = (op>>20) & 0xF;
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o2 = (op>>16) & 0xF;
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vd = (op>>12) & 0xF;
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switch((op>>24) & 0xF){
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default:
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unimp(pc, op);
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case 0xD:
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/*
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* Extension Register load/store A7.6
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*/
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off = (op&0xFF)<<2;
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if((op & (1<<23)) == 0)
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off = -off;
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ea = REG(ur, o2) + off;
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switch(o1&0x7){ /* D(Bit 22) = 0 (5l) */
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default:
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unimp(pc, op);
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case 0:
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if(sz)
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fst(fpii2d, ea, vd, sz, ufp);
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else
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fst(fpii2s, ea, vd, sz, ufp);
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break;
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case 1:
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if(sz)
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fld(fpid2i, vd, ea, sz, ufp);
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else
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fld(fpis2i, vd, ea, sz, ufp);
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break;
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}
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break;
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|
case 0xE:
|
|
if(op & (1<<4)){
|
|
/*
|
|
* Register transfer between Core & Extension A7.8
|
|
*/
|
|
if(sz) /* C(Bit 8) != 0 */
|
|
unimp(pc, op);
|
|
switch(o1){
|
|
default:
|
|
unimp(pc, op);
|
|
case 0: /* Fn := Rt */
|
|
*((Word*)&FR(ufp, o2)) = REG(ur, vd);
|
|
if(fpemudebug)
|
|
print("MOVWF R%d, F%d\n", vd, o2);
|
|
break;
|
|
case 1: /* Rt := Fn */
|
|
REG(ur, vd) = *((Word*)&FR(ufp, o2));
|
|
if(fpemudebug)
|
|
print("MOVFW F%d, R%d =%ld\n", o2, vd, REG(ur, vd));
|
|
break;
|
|
case 0xE: /* FPSCR := Rt */
|
|
ufp->status = REG(ur, vd);
|
|
if(fpemudebug)
|
|
print("MOVW R%d, FPSCR\n", vd);
|
|
break;
|
|
case 0xF: /* Rt := FPSCR */
|
|
if(vd == 0xF){
|
|
ur->psr = ufp->status;
|
|
if(fpemudebug)
|
|
print("MOVW FPSCR, PSR\n");
|
|
}else{
|
|
REG(ur, vd) = ufp->status;
|
|
if(fpemudebug)
|
|
print("MOVW FPSCR, R%d\n", vd);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
else{
|
|
/*
|
|
* VFP data processing instructions A7.5
|
|
* Note: As per 5l we ignore (D, N, M) bits
|
|
*/
|
|
if(fpemudebug)
|
|
tag = 'F';
|
|
o3 = (op>>6) & 0x3;
|
|
o4 = op & 0xF;
|
|
fm = &FR(ufp, o4);
|
|
|
|
if(o1 == 0xB){ /* A7-17 */
|
|
if(o3 & 0x1){
|
|
switch(o2){
|
|
default:
|
|
o = (o2<<1) | (o3>>1);
|
|
break;
|
|
case 0x8: /* CVT int -> float/double */
|
|
w = *((Word*)fm);
|
|
fpiw2i(&FR(ufp, vd), &w);
|
|
if(fpemudebug)
|
|
print("CVTW%c F%d, F%d\n", sz?'D':'F', o4, vd);
|
|
return;
|
|
case 0xD: /* CVT float/double -> int */
|
|
fpii2w(&w, fm);
|
|
*((Word*)&FR(ufp, vd)) = w;
|
|
if(fpemudebug)
|
|
print("CVT%cW F%d, F%d\n", sz?'D':'F', o4, vd);
|
|
return;
|
|
case 0x5: /* CMPF(E) */
|
|
fm = &fpconst[0];
|
|
if(fpemudebug)
|
|
tag = 'C';
|
|
case 0x4: /* CMPF(E) */
|
|
ufp->status &= ~(N|C|Z|V);
|
|
ufp->status |= fcmp(&FR(ufp, vd), fm);
|
|
if(fpemudebug)
|
|
print("CMPF %c%d,F%d =%#lux\n",
|
|
tag, (o2&0x1)? 0: o4, vd, ufp->status>>28);
|
|
return;
|
|
}
|
|
}else{ /* VMOV imm (VFPv3 & v4) (5l doesn't generate) */
|
|
vfpoptoi(&fc, o2, o4);
|
|
fm = &fc;
|
|
o = 0;
|
|
if(fpemudebug)
|
|
tag = 'C';
|
|
}
|
|
FP1 *vfp;
|
|
vfp = &voptab1[o];
|
|
if(vfp->f == nil)
|
|
unimp(pc, op);
|
|
if(fpemudebug)
|
|
print("%s %c%d,F%d\n", vfp->name, tag, o4, vd);
|
|
(*vfp->f)(fm, &FR(ufp, vd));
|
|
}
|
|
else { /* A7-16 */
|
|
FP2 *vfp;
|
|
o = ((o1&0x3)<<1) | (o1&0x8) | (o3&0x1);
|
|
vfp = &voptab2[o];
|
|
if(vfp->f == nil)
|
|
unimp(pc, op);
|
|
if(fpemudebug)
|
|
print("%s F%d,F%d,F%d\n", vfp->name, o4, o2, vd);
|
|
(*vfp->f)(*fm, FR(ufp, o2), &FR(ufp, vd));
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
void
|
|
casemu(ulong pc, ulong op, Ureg *ur)
|
|
{
|
|
ulong *rp, ro, rn, *rd;
|
|
|
|
USED(pc);
|
|
|
|
rp = (ulong*)ur;
|
|
ro = rp[op>>16 & 0x7];
|
|
rn = rp[op>>0 & 0x7];
|
|
rd = rp + (op>>12 & 0x7);
|
|
rp = (ulong*)*rd;
|
|
validaddr((uintptr)rp, 4, 1);
|
|
splhi();
|
|
if(*rd = (*rp == ro))
|
|
*rp = rn;
|
|
spllo();
|
|
}
|
|
|
|
int ldrexvalid;
|
|
|
|
void
|
|
ldrex(ulong pc, ulong op, Ureg *ur)
|
|
{
|
|
ulong *rp, *rd, *addr;
|
|
|
|
USED(pc);
|
|
|
|
rp = (ulong*)ur;
|
|
rd = rp + (op>>16 & 0x7);
|
|
addr = (ulong*)*rd;
|
|
validaddr((uintptr)addr, 4, 0);
|
|
ldrexvalid = 1;
|
|
rp[op>>12 & 0x7] = *addr;
|
|
if(fpemudebug)
|
|
print("ldrex, r%ld = [r%ld]@0x%8.8p = 0x%8.8lux",
|
|
op>>12 & 0x7, op>>16 & 0x7, addr, rp[op>>12 & 0x7]);
|
|
}
|
|
|
|
void
|
|
strex(ulong pc, ulong op, Ureg *ur)
|
|
{
|
|
ulong *rp, rn, *rd, *addr;
|
|
|
|
USED(pc);
|
|
|
|
rp = (ulong*)ur;
|
|
rd = rp + (op>>16 & 0x7);
|
|
rn = rp[op>>0 & 0x7];
|
|
addr = (ulong*)*rd;
|
|
validaddr((uintptr)addr, 4, 1);
|
|
splhi();
|
|
if(ldrexvalid){
|
|
if(fpemudebug)
|
|
print("strex valid, [r%ld]@0x%8.8p = r%ld = 0x%8.8lux",
|
|
op>>16 & 0x7, addr, op>>0 & 0x7, rn);
|
|
*addr = rn;
|
|
ldrexvalid = 0;
|
|
rp[op>>12 & 0x7] = 0;
|
|
}else{
|
|
if(fpemudebug)
|
|
print("strex invalid, r%ld = 1", op>>16 & 0x7);
|
|
rp[op>>12 & 0x7] = 1;
|
|
}
|
|
spllo();
|
|
}
|
|
|
|
struct {
|
|
ulong opc;
|
|
ulong mask;
|
|
void (*f)(ulong, ulong, Ureg*);
|
|
} specialopc[] = {
|
|
{ 0x01900f9f, 0x0ff00fff, ldrex },
|
|
{ 0x01800f90, 0x0ff00ff0, strex },
|
|
{ 0x0ed00100, 0x0ef08100, casemu },
|
|
{ 0x00000000, 0x00000000, nil }
|
|
};
|
|
|
|
/*
|
|
* returns the number of FP instructions emulated
|
|
*/
|
|
int
|
|
fpiarm(Ureg *ur)
|
|
{
|
|
ulong op, o, cp;
|
|
FPsave *ufp;
|
|
int i, n;
|
|
|
|
if(up == nil)
|
|
panic("fpiarm not in a process");
|
|
ufp = up->fpsave;
|
|
/*
|
|
* because all the emulated fp state is in the proc structure,
|
|
* it need not be saved/restored
|
|
*/
|
|
if(up->fpstate != FPactive){
|
|
// assert(sizeof(Internal) == sizeof(ufp->regs[0]));
|
|
up->fpstate = FPactive;
|
|
ufp->control = 0;
|
|
ufp->status = (0x01<<28)|(1<<12); /* software emulation, alternative C flag */
|
|
for(n = 0; n < Nfpctlregs; n++)
|
|
FR(ufp, n) = fpconst[0];
|
|
}
|
|
for(n=0; ;n++){
|
|
validaddr(ur->pc, 4, 0);
|
|
op = *(ulong*)(ur->pc);
|
|
if(fpemudebug)
|
|
print("%#lux: %#8.8lux ", ur->pc, op);
|
|
o = (op>>24) & 0xF;
|
|
cp = (op>>8) & 0xF;
|
|
for(i = 0; specialopc[i].f; i++)
|
|
if((op & specialopc[i].mask) == specialopc[i].opc)
|
|
break;
|
|
if(specialopc[i].f){
|
|
if(condok(ur->psr, op>>28))
|
|
specialopc[i].f(ur->pc, op, ur);
|
|
}
|
|
else if(ISVFPOP(cp, o)){
|
|
if(condok(ur->psr, op>>28))
|
|
vfpemu(ur->pc, op, ur, ufp);
|
|
}
|
|
else if(ISFPAOP(cp, o)){
|
|
if(condok(ur->psr, op>>28))
|
|
fpaemu(ur->pc, op, ur, ufp);
|
|
}
|
|
else
|
|
break;
|
|
|
|
ur->pc += 4; /* pretend cpu executed the instr */
|
|
}
|
|
if(fpemudebug)
|
|
print("\n");
|
|
return n;
|
|
}
|