201 lines
6.1 KiB
C
201 lines
6.1 KiB
C
/*
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* Program Status Registers
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*/
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#define PsrMusr 0x00000010 /* mode */
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#define PsrMfiq 0x00000011
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#define PsrMirq 0x00000012
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#define PsrMsvc 0x00000013
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#define PsrMabt 0x00000017
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#define PsrMund 0x0000001B
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#define PsrMsys 0x0000001F
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#define PsrMask 0x0000001F
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#define PsrDfiq 0x00000040 /* disable FIQ interrupts */
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#define PsrDirq 0x00000080 /* disable IRQ interrupts */
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#define PsrV 0x10000000 /* overflow */
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#define PsrC 0x20000000 /* carry/borrow/extend */
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#define PsrZ 0x40000000 /* zero */
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#define PsrN 0x80000000 /* negative/less than */
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/* instruction decoding */
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#define ISCPOP(op) ((op) == 0xE || ((op) & ~1) == 0xC)
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#define ISFPAOP(cp, op) ((cp) == CpOFPA && ISCPOP(op))
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#define ISVFPOP(cp, op) (((cp) == CpDFP || (cp) == CpFP) && ISCPOP(op))
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/*
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* Coprocessors
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*/
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#define CpOFPA 1 /* ancient 7500 FPA */
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#define CpFP 10 /* float FP, VFP cfg. */
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#define CpDFP 11 /* double FP */
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#define CpSC 15 /* System Control */
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/*
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* opcode 1
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*/
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#define CpDef 0 /* default */
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#define CpL2 1 /* L2 cache operations */
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/*
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* Primary (CRn) CpSC registers.
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*/
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#define CpID 0 /* ID and cache type */
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#define CpCONTROL 1 /* miscellaneous control */
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#define CpTTB 2 /* Translation Table Base */
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#define CpDAC 3 /* Domain Access Control */
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#define CpFSR 5 /* Fault Status */
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#define CpFAR 6 /* Fault Address */
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#define CpCACHE 7 /* cache/write buffer control */
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#define CpTLB 8 /* TLB control */
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#define CpCLD 9 /* Cache Lockdown */
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#define CpTLD 10 /* TLB Lockdown */
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#define CpPID 13 /* Process ID */
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#define CpTESTCFG 15 /* test config. (arm926) */
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/*
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* CpID Secondary (CRm) registers.
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*/
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#define CpIDidct 0
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/*
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* CpID op1==0 opcode2 fields.
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*/
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#define CpIDid 0 /* main ID */
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#define CpIDct 1 /* cache type */
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/*
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* CpCONTROL
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*/
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#define CpCmmu 0x00000001 /* M: MMU enable */
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#define CpCalign 0x00000002 /* A: alignment fault enable */
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#define CpCdcache 0x00000004 /* C: data cache on */
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#define CpCwb 0x00000008 /* W: write buffer turned on */
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#define CpCi32 0x00000010 /* P: 32-bit program space */
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#define CpCd32 0x00000020 /* D: 32-bit data space */
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#define CpCbe 0x00000080 /* B: big-endian operation */
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#define CpCsystem 0x00000100 /* S: system permission */
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#define CpCrom 0x00000200 /* R: ROM permission */
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#define CpCicache 0x00001000 /* I: instruction cache on */
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#define CpChv 0x00002000 /* V: high vectors */
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/*
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* CpCACHE Secondary (CRm) registers and opcode2 fields.
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* In ARM-speak, 'flush' means invalidate and 'clean' means writeback.
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* In arm arch v6, these must be available in user mode:
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* CpCACHEinvi, CpCACHEwait (prefetch flush)
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* CpCACHEwb, CpCACHEwait (DSB: data sync barrier)
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* CpCACHEwb, CpCACHEdmbarr (DMB: data memory barrier)
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*/
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#define CpCACHEintr 0 /* interrupt */
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#define CpCACHEinvi 5 /* instruction */
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#define CpCACHEinvd 6 /* data */
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#define CpCACHEinvu 7 /* unified (I+D) */
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#define CpCACHEwb 10 /* writeback D */
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#define CpCACHEwbu 11 /* writeback U (not 926ejs) */
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#define CpCACHEwbi 14 /* writeback D + invalidate */
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#define CpCACHEwbui 15 /* writeback U + inval (not 926ejs) */
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/*
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* the 926ejs manual says that we can't use CpCACHEall nor CpCACHEwait
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* for writeback operations on the 926ejs, except for CpCACHEwb + CpCACHEwait,
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* which means `drain write buffer'.
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*/
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#define CpCACHEall 0 /* entire */
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#define CpCACHEse 1 /* single entry */
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#define CpCACHEsi 2 /* set/index */
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#define CpCACHEtest 3 /* test loop */
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#define CpCACHEwait 4 /* wait */
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#define CpCACHEdmbarr 5 /* wb: data memory barrier */
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/*
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* CpTLB Secondary (CRm) registers and opcode2 fields.
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*/
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#define CpTLBinvi 5 /* instruction */
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#define CpTLBinvd 6 /* data */
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#define CpTLBinvu 7 /* unified */
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#define CpTLBinv 0 /* invalidate all */
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#define CpTLBinvse 1 /* invalidate single entry */
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/*
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* CpTESTCFG Secondary (CRm) registers and opcode2 fields; sheeva only.
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* opcode1 == CpL2 (1). L2 cache operations block the CPU until finished.
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* Specifically, write-back (clean) blocks until all dirty lines have been
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* drained from the L2 buffers.
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*/
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#define CpTCl2cfg 1
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#define CpTCl2flush 9 /* cpu blocks until flush done */
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#define CpTCl2waylck 10
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#define CpTCl2inv 11
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#define CpTCl2perfctl 12
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#define CpTCl2perfcnt 13
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/* CpTCl2cfg */
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#define CpTCl2conf 0
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/* CpTCl2conf bits */
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#define CpTCldcstream (1<<29) /* D cache streaming switch */
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#define CpTCl2wralloc (1<<28) /* cache write allocate */
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#define CpTCl2prefdis (1<<24) /* l2 cache prefetch disable */
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#define CpTCl2ena (1<<22) /* l2 cache enable */
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/* CpTCl2flush & CpTCl2inv */
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#define CpTCl2all 0
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#define CpTCl2seva 1
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#define CpTCl2way 2
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#define CpTCl2sepa 3
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#define CpTCl2valow 4
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#define CpTCl2vahigh 5 /* also triggers flush or inv */
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/* CpTCl2flush
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#define CpTCecccnt 6 /* ecc error count */
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#define CpTCeccthr 7 /* ecc error threshold */
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/* CpTCl2waylck */
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#define CpTCl2waylock 7
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/* CpTCl2inv */
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#define CpTCl2erraddr 7 /* ecc error address */
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/* CpTCl2perfctl */
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#define CpTCl2perf0ctl 0
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#define CpTCl2perf1ctl 1
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/* CpTCl2perfcnt */
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#define CpTCl2perf0low 0
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#define CpTCl2perf0high 1
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#define CpTCl2perf1low 2
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#define CpTCl2perf1high 3
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/*
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* MMU page table entries.
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* Mbo (0x10) bit is implementation-defined and mandatory on some pre-v7 arms.
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*/
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#define Mbo 0x10 /* must be 1 on earlier arms */
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#define Fault 0x00000000 /* L[12] pte: unmapped */
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#define Coarse (Mbo|1) /* L1 */
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#define Section (Mbo|2) /* L1 1MB */
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#define Fine (Mbo|3) /* L1 */
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#define Large 0x00000001u /* L2 64KB */
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#define Small 0x00000002u /* L2 4KB */
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#define Tiny 0x00000003u /* L2 1KB, deprecated */
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#define Buffered 0x00000004u /* L[12]: write-back not -thru */
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#define Cached 0x00000008u /* L[12] */
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#define Dom0 0
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#define Noaccess 0 /* AP, DAC */
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#define Krw 1 /* AP */
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#define Uro 2 /* AP */
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#define Urw 3 /* AP */
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#define Client 1 /* DAC */
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#define Manager 3 /* DAC */
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#define AP(n, v) F((v), ((n)*2)+4, 2)
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#define L1AP(ap) (AP(3, (ap))) /* in L1, only Sections have AP */
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#define L2AP(ap) (AP(3, (ap))|AP(2, (ap))|AP(1, (ap))|AP(0, (ap))) /* pre-armv7 */
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#define DAC(n, v) F((v), (n)*2, 2)
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#define HVECTORS 0xffff0000 /* addr of vectors */
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