usbehci: import changes from sources (portreset, port handover handling), set interrupt threshold to 1 uframe
cinap_lenrek
parent
c4535df0c4
commit
f0facb2ed8
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@ -15,6 +15,7 @@
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#include "usbehci.h"
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static Ctlr* ctlrs[Nhcis];
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static int maxehci = Nhcis;
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/* Isn't this cap list search in a helper function? */
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static void
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@ -89,9 +90,7 @@ ehcireset(Ctlr *ctlr)
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if(i == 100)
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print("ehci %#p controller reset timed out\n", ctlr->capio);
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}
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/* requesting more interrupts per µframe may miss interrupts */
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opio->cmd |= Citc8; /* 1 intr. per ms */
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opio->cmd |= Citc1; /* 1 intr. per µframe */
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coherence();
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switch(opio->cmd & Cflsmask){
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case Cfls1024:
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@ -202,11 +201,10 @@ scanpci(void)
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* currently, if we enable a second ehci controller,
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* we'll wedge solid after iunlock in init for the second one.
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*/
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if (i > 0) {
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// iprint("usbehci: ignoring controllers after the first, "
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// "at %#p\n", io);
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// ctlrs[i] = nil;
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iprint("usbehci: multiple controllers present\n");
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if (i >= maxehci) {
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iprint("usbehci: ignoring controllers after first %d, "
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"at %#p\n", maxehci, io);
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ctlrs[i] = nil;
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}
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}
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}
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@ -215,12 +213,16 @@ static int
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reset(Hci *hp)
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{
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int i;
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char *s;
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Ctlr *ctlr;
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Ecapio *capio;
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Pcidev *p;
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static Lock resetlck;
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if(getconf("*nousbehci"))
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s = getconf("*maxehci");
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if (s != nil && s[0] >= '0' && s[0] <= '9')
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maxehci = atoi(s);
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if(maxehci == 0 || getconf("*nousbehci"))
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return -1;
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ilock(&resetlck);
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scanpci();
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@ -514,6 +514,9 @@ static Qh*
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qhlinkqh(Qh *qh, Qh *next)
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{
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qh->next = next;
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if(next == nil)
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qh->link = Lterm;
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else
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qh->link = PADDR(next)|Lqh;
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coherence();
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return qh;
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@ -1662,7 +1665,7 @@ portlend(Ctlr *ctlr, int port, char *ss)
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static int
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portreset(Hci *hp, int port, int on)
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{
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ulong s;
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ulong *portscp;
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Eopio *opio;
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Ctlr *ctlr;
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int i;
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@ -1678,31 +1681,35 @@ portreset(Hci *hp, int port, int on)
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qunlock(&ctlr->portlck);
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nexterror();
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}
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s = opio->portsc[port-1];
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dprint("ehci %#p port %d reset; sts %#lux\n", ctlr->capio, port, s);
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portscp = &opio->portsc[port-1];
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dprint("ehci %#p port %d reset; sts %#lux\n", ctlr->capio, port, *portscp);
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ilock(ctlr);
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s &= ~(Psenable|Psreset);
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opio->portsc[port-1] = s | Psreset; /* initiate reset */
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/* Shalted must be zero, else Psreset will stay set */
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if (opio->sts & Shalted)
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iprint("ehci %#p: halted yet trying to reset port\n",
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ctlr->capio);
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*portscp = (*portscp & ~Psenable) | Psreset; /* initiate reset */
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coherence();
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for(i = 0; i < 50; i++){ /* was 10 */
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/*
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* usb 2 spec: reset must finish within 20 ms.
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* linux says spec says it can take 50 ms. for hubs.
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*/
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for(i = 0; *portscp & Psreset && i < 10; i++)
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delay(10);
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if((opio->portsc[port-1] & Psreset) == 0)
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break;
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}
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if (opio->portsc[port-1] & Psreset)
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iprint("ehci %#p: port %d didn't reset after %d ms; sts %#lux\n",
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ctlr->capio, port, i * 10, opio->portsc[port-1]);
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opio->portsc[port-1] &= ~Psreset; /* force appearance of reset done */
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if (*portscp & Psreset)
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iprint("ehci %#p: port %d didn't reset within %d ms; sts %#lux\n",
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ctlr->capio, port, i * 10, *portscp);
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*portscp &= ~Psreset; /* force appearance of reset done */
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coherence();
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delay(10); /* ehci spec: enable within 2 ms. */
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delay(10);
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if((opio->portsc[port-1] & Psenable) == 0)
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if((*portscp & Psenable) == 0)
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portlend(ctlr, port, "full");
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iunlock(ctlr);
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dprint("ehci %#p after port %d reset; sts %#lux\n",
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ctlr->capio, port, opio->portsc[port-1]);
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ctlr->capio, port, *portscp);
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qunlock(&ctlr->portlck);
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poperror();
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return 0;
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@ -2407,15 +2414,18 @@ epio(Ep *ep, Qio *io, void *a, long count, int mustlock)
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ntds++;
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/*
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* Use td tok, not io tok, because of setup packets.
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* Also, if the Td was stalled or active (previous Td
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* was a short packet), we must save the toggle as it is.
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* Also, we must save the next toggle value from the
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* last completed Td (in case of a short packet, or
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* fewer than the requested number of packets in the
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* Td being transferred).
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*/
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if(td->csw & (Tdhalt|Tdactive)){
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if(saved++ == 0) {
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if(td->csw & (Tdhalt|Tdactive))
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saved++;
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else{
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if(!saved){
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io->toggle = td->csw & Tddata1;
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coherence();
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}
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}else{
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tot += td->ndata;
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if(c != nil && (td->csw & Tdtok) == Tdtokin && td->ndata > 0){
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memmove(c, td->data, td->ndata);
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@ -3199,6 +3209,7 @@ init(Hci *hp)
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{
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Ctlr *ctlr;
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Eopio *opio;
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static int ctlrno;
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int i;
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hp->highspeed = 1;
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@ -3218,7 +3229,12 @@ init(Hci *hp)
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opio->cmd |= Case;
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coherence();
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ehcirun(ctlr, 1);
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opio->config = Callmine; /* reclaim all ports */
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/*
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* route all ports by default to only one ehci (the first).
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* it's not obvious how multiple ehcis could work and on some
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* machines, setting Callmine on all ehcis makes the machine seize up.
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*/
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opio->config = (ctlrno == 0 ? Callmine : 0);
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coherence();
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for (i = 0; i < hp->nports; i++)
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@ -3226,6 +3242,7 @@ init(Hci *hp)
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iunlock(ctlr);
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if(ehcidebug > 1)
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dump(hp);
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ctlrno++;
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}
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void
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