merge
commit
d80cf1a4ba
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@ -17,7 +17,6 @@ static int mpeisabus = -1;
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extern int i8259elcr; /* mask of level-triggered interrupts */
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extern int i8259elcr; /* mask of level-triggered interrupts */
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static Apic mpapic[MaxAPICNO+1];
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static Apic mpapic[MaxAPICNO+1];
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static int machno2apicno[MaxAPICNO+1]; /* inverse map: machno -> APIC ID */
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static int machno2apicno[MaxAPICNO+1]; /* inverse map: machno -> APIC ID */
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static Ref mpvnoref; /* unique vector assignment */
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static int mpmachno = 1;
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static int mpmachno = 1;
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static Lock mpphysidlock;
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static Lock mpphysidlock;
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static int mpphysid;
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static int mpphysid;
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@ -705,6 +704,24 @@ mpintrcpu(void)
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return mpapic[i].apicno;
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return mpapic[i].apicno;
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}
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}
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/* hardcoded VectorAPIC and stuff. bad. */
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static int
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allocvector(void)
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{
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static int round = 0, num = 1;
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static Lock l;
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int vno;
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lock(&l);
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if(num >= 24) {
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if(++round >= 8) round = 0;
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num = 1;
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}
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vno = 64 + num++ * 8 + round;
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unlock(&l);
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return vno;
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}
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static int
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static int
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mpintrenablex(Vctl* v, int tbdf)
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mpintrenablex(Vctl* v, int tbdf)
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{
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{
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@ -806,13 +823,7 @@ mpintrenablex(Vctl* v, int tbdf)
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* vector regardless of whether the devices on that pin use
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* vector regardless of whether the devices on that pin use
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* the same IRQ as devices on another pin.
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* the same IRQ as devices on another pin.
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*/
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*/
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vno = VectorAPIC + (incref(&mpvnoref)-1)*8;
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vno = allocvector();
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//print("%s vector %d (imask)\n", v->name, vno);
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if(vno > MaxVectorAPIC){
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print("mpintrenable: vno %d, irq %d, tbdf %uX\n",
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vno, v->irq, tbdf);
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return -1;
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}
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hi = mpintrcpu()<<24;
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hi = mpintrcpu()<<24;
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lo = mpintrinit(bus, aintr->intr, vno, v->irq);
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lo = mpintrinit(bus, aintr->intr, vno, v->irq);
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//print("lo 0x%uX: busno %d intr %d vno %d irq %d elcr 0x%uX\n",
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//print("lo 0x%uX: busno %d intr %d vno %d irq %d elcr 0x%uX\n",
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@ -869,11 +880,7 @@ msiintrenable(Vctl *v)
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break;
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break;
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}
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}
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vno = VectorAPIC + (incref(&mpvnoref)-1)*8;
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vno = allocvector();
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if(vno > MaxVectorAPIC) {
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print("msiintrenable: vno %d\n", vno);
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return -1;
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}
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cpu = mpintrcpu();
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cpu = mpintrcpu();
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pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12));
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pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12));
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pcicfgw32(pci, cap + MSIAddr + 4, 0);
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pcicfgw32(pci, cap + MSIAddr + 4, 0);
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