bcm: simplify reboot code
- synchronize rebootcode installation - handle the 1MB identity map in mmu.c (mmuinit1()) - do not overlap CONFADDR with rebootcode, the non boot processors are parked there. - make REBOOTADDR physical addressfront
cinap_lenrek
parent
0fc2adb43d
commit
b715c39bfa
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@ -237,7 +237,7 @@ cpustart(int cpu)
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mb->clr[cpu].doorbell = 1;
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trapinit();
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clockinit();
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mmuinit1();
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mmuinit1(0);
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timersinit();
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cpuidprint();
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archreset();
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@ -40,8 +40,6 @@
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MOVW $0x10000,R3; \
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MOVW R3,(R2)
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#define PUTC(s)
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/*
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* get cpu id, or zero if armv6
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*/
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@ -45,17 +45,6 @@ TEXT armstart(SB), 1, $-4
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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/*
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* clear mach and page tables
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*/
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MOVW $PADDR(MACHADDR), R1
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MOVW $PADDR(KTZERO), R2
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_ramZ:
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MOVW R0, (R1)
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ADD $4, R1
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CMP R1, R2
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BNE _ramZ
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/*
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* turn SMP on
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* invalidate tlb
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@ -67,6 +56,17 @@ _ramZ:
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/*
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* clear mach and page tables
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*/
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MOVW $PADDR(MACHADDR), R1
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MOVW $PADDR(KTZERO), R2
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_ramZ:
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MOVW R0, (R1)
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ADD $4, R1
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CMP R1, R2
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BNE _ramZ
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/*
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* start stack at top of mach (physical addr)
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* set up page tables for kernel
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@ -96,7 +96,6 @@ _ramZ:
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/*
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* enable caches, mmu, and high vectors
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*/
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MRC CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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ORR $(CpChv|CpCdcache|CpCicache|CpCmmu), R0
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MCR CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
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@ -66,7 +66,7 @@ extern int isaconfig(char*, int, ISAConf*);
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extern void l2cacheuwbinv(void);
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extern void links(void);
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extern void mmuinit(void*);
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extern void mmuinit1(void);
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extern void mmuinit1(int);
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extern void mmuinvalidate(void);
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extern void mmuinvalidateaddr(u32int);
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extern uintptr mmukmap(uintptr, uintptr, usize);
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@ -19,7 +19,7 @@
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* Where configuration info is left for the loaded programme.
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*/
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#define BOOTARGS ((char*)CONFADDR)
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#define BOOTARGSLEN (MACHADDR-CONFADDR)
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#define BOOTARGSLEN (REBOOTADDR-PADDR(CONFADDR))
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#define MAXCONF 64
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#define MAXCONFLINE 160
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@ -301,7 +301,7 @@ main(void)
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pageinit();
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userinit();
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launchinit();
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mmuinit1();
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mmuinit1(0);
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schedinit();
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assert(0); /* shouldn't have returned */
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}
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@ -550,6 +550,35 @@ confinit(void)
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}
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static void
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rebootjump(ulong entry, ulong code, ulong size)
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{
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static void (*f)(ulong, ulong, ulong);
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static Lock lk;
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intrsoff();
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intrcpushutdown();
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/* redo identity map */
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mmuinit1(1);
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lock(&lk);
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if(f == nil){
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/* setup reboot trampoline function */
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f = (void*)REBOOTADDR;
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memmove(f, rebootcode, sizeof(rebootcode));
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cachedwbse(f, sizeof(rebootcode));
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}
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unlock(&lk);
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cacheuwbinv();
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l2cacheuwbinv();
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(*f)(entry, code, size);
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for(;;);
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}
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/*
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* exit kernel either on a panic or user request
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*/
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@ -558,14 +587,8 @@ exit(int)
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{
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cpushutdown();
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splfhi();
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if(m->machno != 0){
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void (*f)(ulong, ulong, ulong) = (void*)REBOOTADDR;
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intrsoff();
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intrcpushutdown();
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cacheuwbinv();
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(*f)(0, 0, 0);
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for(;;);
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}
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if(m->machno != 0)
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rebootjump(0, 0, 0);
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archreboot();
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}
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@ -585,21 +608,14 @@ isaconfig(char *, int, ISAConf *)
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void
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reboot(void *entry, void *code, ulong size)
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{
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void (*f)(ulong, ulong, ulong);
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writeconf();
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if (m->machno != 0) {
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procwired(up, 0);
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sched();
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}
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/* setup reboot trampoline function */
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f = (void*)REBOOTADDR;
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memmove(f, rebootcode, sizeof(rebootcode));
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cachedwbse(f, sizeof(rebootcode));
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cpushutdown();
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delay(500);
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delay(1000);
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splfhi();
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@ -611,14 +627,10 @@ reboot(void *entry, void *code, ulong size)
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/* stop the clock (and watchdog if any) */
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clockshutdown();
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intrsoff();
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intrcpushutdown();
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cacheuwbinv();
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l2cacheuwbinv();
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wdogoff();
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/* off we go - never to return */
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(*f)(PADDR(entry), PADDR(code), size);
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rebootjump(PADDR(entry), PADDR(code), size);
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}
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void
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@ -44,6 +44,7 @@
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#define KSEGM 0xC0000000
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#define KZERO KSEG0 /* kernel address space */
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#define CONFADDR (KZERO+0x100) /* unparsed plan9.ini */
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#define REBOOTADDR (0x1c00) /* reboot code - physical address */
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#define MACHADDR (KZERO+0x2000) /* Mach structure */
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#define L2 (KZERO+0x3000) /* L2 ptes for vectors etc */
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#define VCBUFFER (KZERO+0x3400) /* videocore mailbox buffer */
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@ -62,9 +63,6 @@
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#define TSTKTOP (USTKTOP-USTKSIZE) /* sysexec temporary stack */
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#define TSTKSIZ 256
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/* address at which to copy and execute rebootcode */
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#define REBOOTADDR (KZERO+0x1800)
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/*
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* Legacy...
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*/
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@ -123,8 +123,8 @@ init.h:D: ../port/initcode.c init9.s
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reboot.h:D: rebootcode.s arm.s arm.h mem.h
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$AS rebootcode.s
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# -lc is only for memmove. -T arg is PADDR(REBOOTADDR)
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$LD -l -s -T0x1800 -R4 -o reboot.out rebootcode.$O -lc
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# -lc is only for memmove. -T arg is REBOOTADDR
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$LD -l -s -T0x1c00 -R4 -o reboot.out rebootcode.$O -lc
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{echo 'uchar rebootcode[]={'
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xd -1x reboot.out |
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sed -e '1,2d' -e 's/^[0-9a-f]+ //' -e 's/ ([0-9a-f][0-9a-f])/0x\1,/g'
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@ -12,6 +12,7 @@
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#define L2AP(ap) l2ap(ap)
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#define L1ptedramattrs soc.l1ptedramattrs
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#define L2ptedramattrs soc.l2ptedramattrs
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#define PTEDRAM (PHYSDRAM|Dom0|L1AP(Krw)|Section|L1ptedramattrs)
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enum {
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L1lo = UZERO/MiB, /* L1X(UZERO)? */
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@ -43,7 +44,7 @@ mmuinit(void *a)
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/*
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* identity map first MB of ram so mmu can be enabled
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*/
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l1[L1X(PHYSDRAM)] = PHYSDRAM|Dom0|L1AP(Krw)|Section|L1ptedramattrs;
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l1[L1X(PHYSDRAM)] = PTEDRAM;
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/*
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* map i/o registers
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@ -65,19 +66,19 @@ mmuinit(void *a)
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l2[L2X(va)] = PHYSDRAM|L2AP(Krw)|Small|L2ptedramattrs;
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}
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/*
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* enable/disable identity map of first MB of ram
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*/
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void
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mmuinit1()
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mmuinit1(int on)
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{
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PTE *l1;
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l1 = m->mmul1;
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/*
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* undo identity map of first MB of ram
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*/
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l1[L1X(PHYSDRAM)] = 0;
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l1[L1X(PHYSDRAM)] = on? PTEDRAM: Fault;
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cachedwbtlb(&l1[L1X(PHYSDRAM)], sizeof(PTE));
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mmuinvalidateaddr(PHYSDRAM);
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mmuinvalidate();
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}
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static void
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@ -3,8 +3,6 @@
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*/
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#include "arm.s"
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#define PTEDRAM (Dom0|L1AP(Krw)|Section)
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#define WFI WORD $0xe320f003 /* wait for interrupt */
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#define WFE WORD $0xe320f002 /* wait for event */
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@ -26,8 +24,16 @@ TEXT main(SB), 1, $-4
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MOVW $(PsrDirq|PsrDfiq|PsrMsvc), R1
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MOVW R1, CPSR
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/* prepare to turn off mmu */
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BL cachesoff(SB)
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/* turn caches off */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $(CpCdcache|CpCicache|CpCpredict), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BARRIERS
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/* invalidate icache */
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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BARRIERS
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/* turn off mmu */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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@ -49,7 +55,7 @@ dowfi:
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MOVW $0x40000060, R1
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ADD R2<<2, R1
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MOVW 0(R1), R0
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AND $0x10, R0
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AND $0x10, R0
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BEQ dowfi
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MOVW $0x8000, R1
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BL (R1)
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@ -72,47 +78,3 @@ bootcpu:
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ORR R8,R8
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B (R8)
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B 0(PC)
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/*
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* turn the caches off, double map PHYSDRAM & KZERO, invalidate TLBs, revert
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* to tiny addresses. upon return, it will be safe to turn off the mmu.
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* clobbers R0-R2, and returns with SP invalid.
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*/
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TEXT cachesoff(SB), 1, $-4
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MOVM.DB.W [R14,R1-R10], (R13) /* save regs on stack */
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/* turn caches off, invalidate icache */
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MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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BIC $(CpCdcache|CpCicache|CpCpredict), R1
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MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
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/* invalidate stale TLBs before changing them */
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BARRIERS
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* redo double map of first MiB PHYSDRAM = KZERO */
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MOVW 12(R(MACH)), R2 /* m->mmul1 (virtual addr) */
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MOVW $PTEDRAM, R1 /* PTE bits */
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MOVW R1, (R2)
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DSB
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MCR CpSC, 0, R2, C(CpCACHE), C(CpCACHEwb), CpCACHEse
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/* invalidate stale TLBs again */
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BARRIERS
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MOVW $0, R0
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MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
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BARRIERS
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/* relocate SB and return address to PHYSDRAM addressing */
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MOVW $KSEGM, R1 /* clear segment bits */
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BIC R1, R12 /* adjust SB */
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MOVM.IA.W (R13), [R14,R1-R10] /* restore regs from stack */
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MOVW $KSEGM, R1 /* clear segment bits */
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BIC R1, R14 /* adjust return address */
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RET
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