ether8169: fix interrupt panic before init, defer initialization until attach
The driver used to register the interrupt handler just after reset, tho the Ctlr struct, including the buffer descriptor arrays where only allocated on attach. This moves most of the reset/init out of pnp function and into attach. This also means we can error out and even retry on the next attach. The logic of the reseter kproc has been changed: now it is only started once the first initialization completely succeeded. This avoids the strange qlock passing. Implement a shutdown function so the device gets halted for /dev/reboot. Assume 64 bit physical addresses for dma. Check that pci bar0 is actually I/O.front
cinap_lenrek
parent
0f56fefd45
commit
b438fd9d09
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@ -383,16 +383,16 @@ rtl8169miimiw(Mii* mii, int pa, int ra, int data)
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return 0;
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}
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static int
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rtl8169mii(Ctlr* ctlr)
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static void
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rtl8169mii(Ether *edev)
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{
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Ctlr *ctlr = edev->ctlr;
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MiiPhy *phy;
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/*
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* Link management.
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*/
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if((ctlr->mii = malloc(sizeof(Mii))) == nil)
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return -1;
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ctlr->mii = smalloc(sizeof(Mii));
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ctlr->mii->mir = rtl8169miimir;
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ctlr->mii->miw = rtl8169miimiw;
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ctlr->mii->ctlr = ctlr;
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@ -420,22 +420,20 @@ rtl8169mii(Ctlr* ctlr)
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csr8w(ctlr, Ldps, 1); /* magic */
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rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */
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}
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if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
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free(ctlr->mii);
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ctlr->mii = nil;
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return -1;
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error("no phy");
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return;
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}
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print("rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
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phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
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print("#l%d: rtl8169: oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
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edev->ctlrno, phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
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miireset(ctlr->mii);
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microdelay(100);
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miiane(ctlr->mii, ~0, ~0, ~0);
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return 0;
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}
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static void
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@ -615,6 +613,8 @@ static void
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rtl8169halt(Ctlr* ctlr)
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{
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csr8w(ctlr, Cr, 0);
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ctlr->imr = 0;
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csr16w(ctlr, Imr, 0);
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csr16w(ctlr, Isr, ~0);
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}
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@ -648,6 +648,7 @@ rtl8169replenish(Ctlr* ctlr)
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D *d;
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int x;
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Block *bp;
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u64int pa;
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x = ctlr->rdt;
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while(NEXT(x, ctlr->nrd) != ctlr->rdh){
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@ -658,9 +659,10 @@ rtl8169replenish(Ctlr* ctlr)
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}
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ctlr->rb[x] = bp;
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ctlr->nrq++;
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pa = PCIWADDR(bp->rp);
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d = &ctlr->rd[x];
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d->addrlo = PCIWADDR(bp->rp);
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d->addrhi = 0;
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d->addrlo = pa;
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d->addrhi = pa >> 32;
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coherence();
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d->control = (d->control & Eor) | Own | BALLOC(bp);
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x = NEXT(x, ctlr->nrd);
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@ -668,19 +670,22 @@ rtl8169replenish(Ctlr* ctlr)
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}
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}
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static int
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static void
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rtl8169init(Ether* edev)
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{
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int i;
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u32int r;
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Block *bp;
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Ctlr *ctlr;
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u64int pa;
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u16int cplusc;
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ctlr = edev->ctlr;
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ilock(ctlr);
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rtl8169reset(ctlr);
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if(rtl8169reset(ctlr) < 0){
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iunlock(ctlr);
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error("reset failed");
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}
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memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
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ctlr->tdh = ctlr->tdt = ctlr->ntq = 0;
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@ -716,10 +721,13 @@ rtl8169init(Ether* edev)
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}
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csr16w(ctlr, Cplusc, cplusc);
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csr32w(ctlr, Tnpds+4, 0);
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csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
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csr32w(ctlr, Rdsar+4, 0);
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csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
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pa = PCIWADDR(ctlr->td);
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csr32w(ctlr, Tnpds+4, pa>>32);
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csr32w(ctlr, Tnpds, pa);
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pa = PCIWADDR(ctlr->rd);
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csr32w(ctlr, Rdsar+4, pa>>32);
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csr32w(ctlr, Rdsar, pa);
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csr8w(ctlr, Cr, Te|Re);
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@ -755,8 +763,6 @@ rtl8169init(Ether* edev)
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csr32w(ctlr, Mpc, 0);
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iunlock(ctlr);
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return 0;
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}
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static void
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@ -766,69 +772,80 @@ rtl8169reseter(void *arg)
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Ctlr *ctlr;
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edev = arg;
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while(waserror())
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;
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for(;;){
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rtl8169init(edev);
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ctlr = edev->ctlr;
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qunlock(&ctlr->alock);
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while(waserror())
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;
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sleep(&ctlr->reset, return0, nil);
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poperror();
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qlock(&ctlr->alock);
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rtl8169init(edev);
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}
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}
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static void rtl8169interrupt(Ureg*, void* arg);
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static void
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rtl8169attach(Ether* edev)
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{
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int timeo;
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Ctlr *ctlr;
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ctlr = edev->ctlr;
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qlock(&ctlr->alock);
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if(!ctlr->init){
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ctlr->ntd = Ntd;
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ctlr->nrd = Nrd;
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ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
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ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
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ctlr->td = mallocalign(sizeof(D)*ctlr->ntd, 256, 0, 0);
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ctlr->rd = mallocalign(sizeof(D)*ctlr->nrd, 256, 0, 0);
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ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
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if(ctlr->rb == nil || ctlr->rb == nil ||
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ctlr->rd == nil || ctlr->rd == nil || ctlr->dtcc == nil){
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free(ctlr->tb);
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ctlr->tb = nil;
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free(ctlr->rb);
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ctlr->rb = nil;
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free(ctlr->td);
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ctlr->td = nil;
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free(ctlr->rd);
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ctlr->rd = nil;
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free(ctlr->dtcc);
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ctlr->dtcc = nil;
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qunlock(&ctlr->alock);
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error(Enomem);
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}
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ctlr->init = 1;
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kproc("rtl8169", rtl8169reseter, edev);
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/* rtl8169reseter() does qunlock(&ctlr->alock) when complete */
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qlock(&ctlr->alock);
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if(ctlr->init){
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qunlock(&ctlr->alock);
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return;
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}
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if(waserror()){
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print("#l%d: rtl8169: %s\n", edev->ctlrno, up->errstr);
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qunlock(&ctlr->alock);
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nexterror();
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}
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ctlr->ntd = Ntd;
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ctlr->nrd = Nrd;
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ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
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ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
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ctlr->td = mallocalign(sizeof(D)*ctlr->ntd, 256, 0, 0);
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ctlr->rd = mallocalign(sizeof(D)*ctlr->nrd, 256, 0, 0);
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ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
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if(waserror()){
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free(ctlr->tb);
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ctlr->tb = nil;
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free(ctlr->rb);
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ctlr->rb = nil;
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free(ctlr->td);
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ctlr->td = nil;
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free(ctlr->rd);
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ctlr->rd = nil;
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free(ctlr->dtcc);
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ctlr->dtcc = nil;
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nexterror();
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}
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if(ctlr->tb == nil || ctlr->rb == nil
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|| ctlr->td == nil || ctlr->rd == nil
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|| ctlr->dtcc == nil)
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error(Enomem);
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pcisetbme(ctlr->pcidev);
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intrenable(edev->irq, rtl8169interrupt, edev, edev->tbdf, edev->name);
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if(waserror()){
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rtl8169halt(ctlr);
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pciclrbme(ctlr->pcidev);
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intrdisable(edev->irq, rtl8169interrupt, edev, edev->tbdf, edev->name);
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nexterror();
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}
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rtl8169init(edev);
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rtl8169mii(edev);
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ctlr->init = 1;
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poperror();
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poperror();
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kproc("rtl8169", rtl8169reseter, edev);
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qunlock(&ctlr->alock);
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/*
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* Wait for link to be ready.
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*/
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for(timeo = 0; timeo < 35; timeo++){
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if(miistatus(ctlr->mii) == 0)
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break;
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delay(100); /* print fewer miistatus messages */
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}
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poperror();
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}
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static void
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@ -866,6 +883,7 @@ rtl8169transmit(Ether* edev)
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D *d;
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Block *bp;
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Ctlr *ctlr;
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u64int pa;
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int x;
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ctlr = edev->ctlr;
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@ -894,9 +912,10 @@ rtl8169transmit(Ether* edev)
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if((bp = qget(edev->oq)) == nil)
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break;
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pa = PCIWADDR(bp->rp);
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d = &ctlr->td[x];
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d->addrlo = PCIWADDR(bp->rp);
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d->addrhi = 0;
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d->addrlo = pa;
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d->addrhi = pa >> 32;
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coherence();
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d->control = (d->control & Eor) | Own | Fs | Ls | BLEN(bp);
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@ -990,7 +1009,6 @@ rtl8169receive(Ether* edev)
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static void
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rtl8169restart(Ctlr *ctlr)
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{
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ctlr->imr = 0;
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rtl8169halt(ctlr);
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wakeup(&ctlr->reset);
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}
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@ -1037,6 +1055,14 @@ rtl8169interrupt(Ureg*, void* arg)
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}
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}
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static void
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rtl8169shutdown(Ether *edev)
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{
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Ctlr *ctlr = edev->ctlr;
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rtl8169halt(ctlr);
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}
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int
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vetmacv(Ctlr *ctlr, uint *macv)
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{
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@ -1103,11 +1129,14 @@ rtl8169pci(void)
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break;
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}
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if(p->mem[0].size == 0 || (p->mem[0].bar & 1) == 0)
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continue;
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port = p->mem[0].bar & ~3;
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if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
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print("rtl8169: port %#ux in use\n", port);
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continue;
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}
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ctlr = malloc(sizeof(Ctlr));
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if(ctlr == nil){
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print("rtl8169: can't allocate memory\n");
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@ -1121,31 +1150,19 @@ rtl8169pci(void)
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pcienable(p);
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if(vetmacv(ctlr, &macv) == -1){
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print("rtl8169: %T: unknown mac %.4ux %.8ux\n", p->tbdf, p->did, macv);
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pcidisable(p);
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iofree(port);
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free(ctlr);
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print("rtl8169: unknown mac %.4ux %.8ux\n", p->did, macv);
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continue;
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}
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if(rtl8169reset(ctlr)){
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pcidisable(p);
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iofree(port);
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free(ctlr);
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print("rtl8169: reset failed\n");
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continue;
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}
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rtl8169halt(ctlr);
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/*
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* Extract the chip hardware version,
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* needed to configure each properly.
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*/
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ctlr->macv = macv;
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rtl8169mii(ctlr);
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pcisetbme(p);
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if(rtl8169ctlrhead != nil)
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rtl8169ctlrtail->next = ctlr;
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else
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@ -1208,6 +1225,7 @@ rtl8169pnp(Ether* edev)
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edev->attach = rtl8169attach;
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edev->transmit = rtl8169transmit;
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edev->ifstat = rtl8169ifstat;
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edev->shutdown = rtl8169shutdown;
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edev->arg = edev;
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edev->promiscuous = rtl8169promiscuous;
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@ -1215,8 +1233,6 @@ rtl8169pnp(Ether* edev)
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rtl8169link(edev);
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intrenable(edev->irq, rtl8169interrupt, edev, edev->tbdf, edev->name);
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return 0;
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}
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