mp: cleanup allocvector, allow sharing of edge triggered interrupts, more southbridges
cinap_lenrek
parent
b3d47c3a3a
commit
6e8d0bf500
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@ -259,7 +259,6 @@ mpintrinit(Bus* bus, PCMPintr* intr, int vno, int /*irq*/)
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el = intr->flags & PcmpELMASK;
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switch(intr->intr){
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default: /* PcmpINT */
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v |= ApicFIXED; /* no-op */
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break;
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@ -598,7 +597,6 @@ mpinit(void)
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if(getconf("*mp") != nil)
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mpoverride(&p, &e);
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while(p < e) switch(*p){
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default:
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print("mpinit: unknown PCMP type 0x%uX (e-p 0x%luX)\n",
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*p, e-p);
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@ -738,20 +736,32 @@ mpintrcpu(void)
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return mpapic[i].apicno;
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}
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/* hardcoded VectorAPIC and stuff. bad. */
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/*
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* With the APIC a unique vector can be assigned to each
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* request to enable an interrupt. There are two reasons this
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* is a good idea:
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* 1) to prevent lost interrupts, no more than 2 interrupts
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* should be assigned per block of 16 vectors (there is an
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* in-service entry and a holding entry for each priority
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* level and there is one priority level per block of 16
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* interrupts).
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* 2) each input pin on the IOAPIC will receive a different
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* vector regardless of whether the devices on that pin use
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* the same IRQ as devices on another pin.
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*/
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static int
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allocvector(void)
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{
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static int round = 0, num = 1;
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static int round = 0, num = 0;
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static Lock l;
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int vno;
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lock(&l);
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if(num >= 24) {
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if(++round >= 8) round = 0;
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num = 1;
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}
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vno = 64 + num++ * 8 + round;
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vno = VectorAPIC + num;
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if(vno < MaxVectorAPIC-7)
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num += 8;
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else
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num = ++round % 8;
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unlock(&l);
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return vno;
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}
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@ -780,7 +790,7 @@ mpintrenablex(Vctl* v, int tbdf)
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break;
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}
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if(bus == nil){
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print("ioapicirq: can't find bus type %d, number %d\n", type, bno);
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print("mpintrenable: can't find bus type %d, number %d\n", type, bno);
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return -1;
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}
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@ -796,7 +806,6 @@ mpintrenablex(Vctl* v, int tbdf)
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irq = (dno<<2)|(n-1);
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else
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irq = -1;
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//print("pcidev %uX: irq %uX v->irq %uX\n", tbdf, irq, v->irq);
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}
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else
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irq = v->irq;
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@ -808,9 +817,8 @@ mpintrenablex(Vctl* v, int tbdf)
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for(aintr = bus->aintr; aintr; aintr = aintr->next){
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if(aintr->intr->irq != irq)
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continue;
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if (0) {
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if(0){
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PCMPintr* p = aintr->intr;
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print("mpintrenablex: bus %d intin %d irq %d\n",
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p->busno, p->intin, p->irq);
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}
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@ -828,55 +836,34 @@ mpintrenablex(Vctl* v, int tbdf)
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ioapicrdtr(apic, aintr->intr->intin, 0, &lo);
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if(!(lo & ApicIMASK)){
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vno = lo & 0xFF;
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//print("%s vector %d (!imask)\n", v->name, vno);
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if(0) print("%s vector %d (!imask)\n", v->name, vno);
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n = mpintrinit(bus, aintr->intr, vno, v->irq);
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n |= ApicPHYSICAL; /* no-op */
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lo &= ~(ApicRemoteIRR|ApicDELIVS);
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if(n != lo || !(n & ApicLEVEL)){
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if(n != lo){
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print("mpintrenable: multiple botch irq %d, tbdf %uX, lo %8.8uX, n %8.8uX\n",
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v->irq, tbdf, lo, n);
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return -1;
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}
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v->isr = lapicisr;
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v->eoi = lapiceoi;
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return vno;
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}
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/*
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* With the APIC a unique vector can be assigned to each
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* request to enable an interrupt. There are two reasons this
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* is a good idea:
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* 1) to prevent lost interrupts, no more than 2 interrupts
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* should be assigned per block of 16 vectors (there is an
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* in-service entry and a holding entry for each priority
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* level and there is one priority level per block of 16
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* interrupts).
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* 2) each input pin on the IOAPIC will receive a different
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* vector regardless of whether the devices on that pin use
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* the same IRQ as devices on another pin.
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*/
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vno = allocvector();
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hi = mpintrcpu()<<24;
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lo = mpintrinit(bus, aintr->intr, vno, v->irq);
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//print("lo 0x%uX: busno %d intr %d vno %d irq %d elcr 0x%uX\n",
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// lo, bus->busno, aintr->intr->irq, vno,
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// v->irq, i8259elcr);
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if(lo & ApicIMASK)
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return -1;
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lo |= ApicPHYSICAL; /* no-op */
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if(lo & ApicIMASK){
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print("mpintrenable: disabled irq %d, tbdf %uX, lo %8.8uX, hi %8.8uX\n",
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v->irq, tbdf, lo, hi);
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return -1;
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}
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if((apic->flags & PcmpEN) && apic->type == PcmpIOAPIC)
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ioapicrdtw(apic, aintr->intr->intin, hi, lo);
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//else
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// print("lo not enabled 0x%uX %d\n",
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// apic->flags, apic->type);
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v->isr = lapicisr;
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v->eoi = lapiceoi;
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return vno;
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}
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@ -903,7 +890,7 @@ msiintrenable(Vctl *v)
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return -1;
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pci = pcimatchtbdf(tbdf);
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if(pci == nil) {
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print("msiintrenable: could not find Pcidev for tbdf %.8x\n", tbdf);
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print("msiintrenable: could not find Pcidev for tbdf %uX\n", tbdf);
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return -1;
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}
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cap = pcicap(pci, PciCapMSI);
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@ -916,7 +903,6 @@ msiintrenable(Vctl *v)
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if(ok64) pcicfgw32(pci, cap + MSIAddr + 4, 0);
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pcicfgw16(pci, cap + (ok64 ? MSIData64 : MSIData32), vno | (1<<14));
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pcicfgw16(pci, cap + MSICtrl, 1);
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print("msiintrenable: success with tbdf %.8x, vector %d, cpu %d\n", tbdf, vno, cpu);
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v->isr = lapicisr;
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v->eoi = lapiceoi;
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return vno;
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@ -973,7 +959,7 @@ mpintrenable(Vctl* v)
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if(vno != -1)
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return vno;
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}
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print("mpintrenable: out of choices eisa %d isa %d tbdf %#ux irq %d\n",
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print("mpintrenable: out of choices eisa %d isa %d tbdf %uX irq %d\n",
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mpeisabus, mpisabus, v->tbdf, v->irq);
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return -1;
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}
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@ -658,6 +658,12 @@ static Bridge southbridges[] = {
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{ 0x8086, 0x2670, pIIxget, pIIxset }, /* Intel 632xesb */
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{ 0x8086, 0x27b8, pIIxget, pIIxset }, /* Intel 82801GB */
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{ 0x8086, 0x27b9, pIIxget, pIIxset }, /* Intel 82801GBM */
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{ 0x8086, 0x27bd, pIIxget, pIIxset }, /* Intel 82801GB/GR */
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{ 0x8086, 0x3a16, pIIxget, pIIxset }, /* Intel 82801JIR */
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{ 0x8086, 0x3a40, pIIxget, pIIxset }, /* Intel 82801JI */
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{ 0x8086, 0x3a42, pIIxget, pIIxset }, /* Intel 82801JI */
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{ 0x8086, 0x3a48, pIIxget, pIIxset }, /* Intel 82801JI */
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{ 0x8086, 0x2916, pIIxget, pIIxset }, /* Intel 82801? */
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{ 0x8086, 0x2810, pIIxget, pIIxset }, /* Intel 82801HB/HR (ich8/r) */
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{ 0x8086, 0x2812, pIIxget, pIIxset }, /* Intel 82801HH (ich8dh) */
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{ 0x8086, 0x2912, pIIxget, pIIxset }, /* Intel 82801ih ich9dh */
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@ -672,6 +678,7 @@ static Bridge southbridges[] = {
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{ 0x8086, 0x3a48, pIIxget, pIIxset }, /* Intel 82801ji */
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{ 0x8086, 0x3b06, pIIxget, pIIxset }, /* Intel 82801? ibex peak */
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{ 0x8086, 0x3b14, pIIxget, pIIxset }, /* Intel 82801? 3420 */
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{ 0x8086, 0x1c52, pIIxget, pIIxset }, /* Intel 82q65 cougar point pch */
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{ 0x8086, 0x1c54, pIIxget, pIIxset }, /* Intel 82q67 cougar point pch */
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{ 0x1106, 0x0586, viaget, viaset }, /* Viatech 82C586 */
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{ 0x1106, 0x0596, viaget, viaset }, /* Viatech 82C596 */
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@ -684,15 +691,16 @@ static Bridge southbridges[] = {
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{ 0x1039, 0x0496, pIIxget, pIIxset }, /* SI 496 */
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{ 0x1078, 0x0100, cyrixget, cyrixset }, /* Cyrix 5530 Legacy */
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{ 0x1022, 0x746B, nil, nil }, /* AMD 8111 */
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{ 0x10DE, 0x00D1, nil, nil }, /* NVIDIA nForce 3 */
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{ 0x10DE, 0x00E0, nil, nil }, /* NVIDIA nForce 3 250 Series */
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{ 0x10DE, 0x00E1, nil, nil }, /* NVIDIA nForce 3 250 Series */
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{ 0x1022, 0x746b, nil, nil }, /* AMD 8111 */
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{ 0x10de, 0x00d1, nil, nil }, /* NVIDIA nForce 3 */
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{ 0x10de, 0x00e0, nil, nil }, /* NVIDIA nForce 3 250 Series */
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{ 0x10de, 0x00e1, nil, nil }, /* NVIDIA nForce 3 250 Series */
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{ 0x1166, 0x0200, nil, nil }, /* ServerWorks ServerSet III LE */
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{ 0x1002, 0x4377, nil, nil }, /* ATI Radeon Xpress 200M */
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{ 0x1002, 0x4372, nil, nil }, /* ATI SB400 */
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{ 0x1002, 0x9601, nil, nil }, /* AMD SB710 */
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{ 0x1002, 0x438D, nil, nil }, /* AMD SB600 */
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{ 0x1002, 0x438d, nil, nil }, /* AMD SB600 */
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{ 0x1002, 0x439d, nil, nil }, /* AMD SB810 */
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};
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typedef struct Slot Slot;
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@ -986,7 +994,7 @@ pcicfginit(void)
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fmtinstall('T', tbdffmt);
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if(p = getconf("*pcimaxbno"))
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pcimaxbno = strtoul(p, 0, 0) & 0xff;
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pcimaxbno = strtoul(p, 0, 0);
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if(p = getconf("*pcimaxdno")){
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n = strtoul(p, 0, 0);
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if(n < pcimaxdno)
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