etherbcm: endian word swap
parent
3bd600c01e
commit
663240a9ae
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@ -50,9 +50,11 @@ enum {
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MiscHostCtl = 0x68,
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ClearIntA = 1<<0,
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MaskPCIInt = 1<<1,
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IndirectAccessEnable = 1<<7,
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ByteSwap = 1<<2,
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WordSwap = 1<<3,
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EnablePCIStateRegister = 1<<4,
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EnableClockControlRegister = 1<<5,
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IndirectAccessEnable = 1<<7,
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TaggedStatus = 1<<9,
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DMARWControl = 0x6C,
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@ -300,6 +302,7 @@ replenish(Ctlr *ctlr)
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next[1] = PADDR(bp->rp);
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next[2] = Rbsz;
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next[7] = (ulong) bp;
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coherence();
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csr32(ctlr, RecvProdBDRingIndex) = ctlr->recvprodi = incr;
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return 0;
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}
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@ -369,6 +372,7 @@ bcmtransmit(Ether *edev)
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if(ctlr->sends[ctlr->sendri] != 0)
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freeb(ctlr->sends[ctlr->sendri]);
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ctlr->sends[ctlr->sendri] = bp;
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coherence();
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csr32(ctlr, SendBDRingHostIndex) = ctlr->sendri = incr;
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}
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iunlock(&ctlr->txlock);
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@ -444,15 +448,18 @@ bcminit(Ether *edev)
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}
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csr32(ctlr, MemArbiterMode) |= Enable;
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csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister;
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csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
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csr32(ctlr, ModeControl) |= ByteWordSwap;
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csr32(ctlr, MemoryWindow) = 0;
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mem32(ctlr, 0xB50) = 0x4B657654; /* magic number bullshit */
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csr32(ctlr, MiscConfiguration) |= GPHYPowerDownOverride | DisableGRCResetOnPCIE;
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csr32(ctlr, MiscConfiguration) |= CoreClockBlocksReset;
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microdelay(100000);
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ctlr->pdev->pcr |= 1<<1;
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ctlr->pdev->pcr |= 1<<1; /* pci memory access enable */
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pcisetbme(ctlr->pdev);
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csr32(ctlr, MiscHostCtl) |= MaskPCIInt;
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csr32(ctlr, MemArbiterMode) |= Enable;
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csr32(ctlr, MiscHostCtl) = (csr32(ctlr, MiscHostCtl) & ~(ByteSwap|WordSwap)) | WordSwap;
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csr32(ctlr, MiscHostCtl) |= IndirectAccessEnable | EnablePCIStateRegister | EnableClockControlRegister | TaggedStatus;
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csr32(ctlr, ModeControl) |= ByteWordSwap;
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csr32(ctlr, MACMode) = (csr32(ctlr, MACMode) & MACPortMask) | MACPortGMII;
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