7l: fix bitcon instruction selection and encoding
the possible bitmasks generated depend on the data width of the instruction, so we introduce C_BITCON32 and C_BITCON64 operand types to keep them apart. the encoding of the bitcon operation was wrong.front
cinap_lenrek
parent
d8d4802f80
commit
12fc1c7d3e
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@ -722,27 +722,24 @@ asmout(Prog *p, Optab *o)
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if(as == AMOV){
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as = AORR;
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r = REGZERO;
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}else if(as == AMOVW){
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}else if(as == AMOVW || as == AMOVWU){
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as = AORRW;
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r = REGZERO;
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}
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o1 = opirr(as);
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s = o1 & S64? 64: 32;
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mask = findmask(p->from.offset);
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if(mask == nil)
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mask = findmask(p->from.offset | (p->from.offset<<32));
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if(mask != nil){
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o1 |= ((mask->r&(s-1))<<16) | (((mask->s-1)&(s-1))<<10);
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if(s == 64){
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if(mask->e == 64 && ((uvlong)p->from.offset>>32) != 0)
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o1 |= 1<<22;
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}else{
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u = (uvlong)p->from.offset >> 32;
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if(u != 0 && u != 0xFFFFFFFF)
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diag("mask needs 64 bits %#llux\n%P", p->from.offset, p);
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}
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}else
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diag("invalid mask %#llux\n%P", p->from.offset, p); /* probably shouldn't happen */
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mask = findmask(p->from.offset | p->from.offset<<32);
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if(mask == nil)
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diag("invalid mask %#llux\n%P", p->from.offset, p);
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switch(mask->e){
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case 2: o1 |= 0xF000; break;
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case 4: o1 |= 0xE000; break;
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case 8: o1 |= 0xC000; break;
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case 16: o1 |= 0x8000; break;
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case 64: o1 |= ((o1&S64)!=0)<<22; break;
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}
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o1 |= (mask->r<<16) | ((mask->s-1)<<10);
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o1 |= (r<<5) | rt;
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break;
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@ -1591,7 +1588,7 @@ oaddi(long o1, long v, int r, int rt)
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}
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/*
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* load a a literal value into dr
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* load a literal value into dr
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*/
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static long
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omovlit(int as, Prog *p, Adr *a, int dr)
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@ -158,7 +158,9 @@ enum
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C_ADDCON0, /* 12-bit unsigned, unshifted */
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C_ADDCON, /* 12-bit unsigned, shifted left by 0 or 12 */
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C_MOVCON, /* generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 */
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C_BITCON, /* bimm32 */
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C_BITCON, /* bimm32/bimm64 */
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C_BITCON32, /* bimm32 */
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C_BITCON64, /* bimm64 */
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C_ABCON, /* could be C_ADDCON or C_BITCON */
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C_MBCON, /* could be C_MOVCON or C_BITCON */
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C_LCON, /* 32-bit constant */
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@ -42,25 +42,42 @@ Optab optab[] =
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/* logical operations */
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{ AAND, C_REG, C_REG, C_REG, 1, 4, 0 },
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{ AANDW, C_REG, C_REG, C_REG, 1, 4, 0 },
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{ AAND, C_REG, C_NONE, C_REG, 1, 4, 0 },
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{ AANDW, C_REG, C_NONE, C_REG, 1, 4, 0 },
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{ ABIC, C_REG, C_REG, C_REG, 1, 4, 0 },
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{ ABICW, C_REG, C_REG, C_REG, 1, 4, 0 },
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{ ABIC, C_REG, C_NONE, C_REG, 1, 4, 0 },
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{ ABICW, C_REG, C_NONE, C_REG, 1, 4, 0 },
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{ AAND, C_BITCON, C_REG, C_REG, 53, 4, 0 },
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{ AAND, C_BITCON, C_NONE, C_REG, 53, 4, 0 },
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{ ABIC, C_BITCON, C_REG, C_REG, 53, 4, 0 },
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{ ABIC, C_BITCON, C_NONE, C_REG, 53, 4, 0 },
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{ AAND, C_BITCON64,C_REG,C_REG, 53, 4, 0 },
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{ AANDW, C_BITCON32,C_REG,C_REG, 53, 4, 0 },
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{ AAND, C_BITCON64,C_NONE,C_REG, 53, 4, 0 },
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{ AANDW, C_BITCON32,C_NONE,C_REG, 53, 4, 0 },
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{ ABIC, C_BITCON64,C_REG,C_REG, 53, 4, 0 },
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{ ABICW, C_BITCON32,C_REG,C_REG, 53, 4, 0 },
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{ ABIC, C_BITCON64,C_NONE,C_REG, 53, 4, 0 },
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{ ABICW, C_BITCON32,C_NONE,C_REG, 53, 4, 0 },
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{ AAND, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
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{ AANDW, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
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{ AAND, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
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{ AANDW, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
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{ ABIC, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
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{ ABICW, C_LCON, C_REG, C_REG, 28, 8, 0, LFROM },
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{ ABIC, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
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{ ABICW, C_LCON, C_NONE, C_REG, 28, 8, 0, LFROM },
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{ AAND, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
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{ AANDW, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
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{ AAND, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
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{ AANDW, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
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{ ABIC, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
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{ ABICW, C_SHIFT,C_REG, C_REG, 3, 4, 0 },
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{ ABIC, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
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{ ABICW, C_SHIFT,C_NONE, C_REG, 3, 4, 0 },
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/* moves */
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{ AMOV, C_RSP, C_NONE, C_RSP, 24, 4, 0 },
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{ AMVN, C_REG, C_NONE, C_REG, 24, 4, 0 },
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{ AMOVB, C_REG, C_NONE, C_REG, 45, 4, 0 },
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@ -70,12 +87,13 @@ Optab optab[] =
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/* TO DO: MVN C_SHIFT */
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/* MOVs that become MOVK/MOVN/MOVZ/ADD/SUB/OR */
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{ AMOVW, C_MOVCON, C_NONE, C_REG, 32, 4, 0 },
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{ AMOVW, C_MOVCON, C_NONE, C_REG, 32, 4, 0 },
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{ AMOV, C_MOVCON, C_NONE, C_REG, 32, 4, 0 },
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// { AMOVW, C_ADDCON, C_NONE, C_REG, 2, 4, 0 },
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// { AMOVW, C_ADDCON, C_NONE, C_REG, 2, 4, 0 },
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// { AMOV, C_ADDCON, C_NONE, C_REG, 2, 4, 0 },
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// { AMOVW, C_BITCON, C_NONE, C_REG, 53, 4, 0 },
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// { AMOV, C_BITCON, C_NONE, C_REG, 53, 4, 0 },
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{ AMOV, C_BITCON64, C_NONE, C_REG, 53, 4, 0 },
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{ AMOVW, C_BITCON32, C_NONE, C_REG, 53, 4, 0 },
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{ AMOVK, C_LCON, C_NONE, C_REG, 33, 4, 0 },
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@ -7,7 +7,7 @@ static struct {
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ulong size;
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} pool;
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static void checkpool(Prog*, int);
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static void checkpool(Prog*, int);
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static void flushpool(Prog*, int);
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static int ispcdisp(long);
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@ -329,11 +329,31 @@ isaddcon(vlong v)
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return v <= 0xFFF;
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}
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static int
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isbitcon64(uvlong v)
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{
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return findmask(v) != nil;
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}
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static int
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isbitcon32(uvlong v)
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{
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return (v >> 32) == 0 && findmask(v | v<<32) != nil;
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}
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static int
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isbitcon(uvlong v)
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{
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/* fancy bimm32 or bimm64? */
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return findmask(v) != nil || (v>>32) == 0 && findmask(v | (v<<32)) != nil;
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Mask *m;
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if((v >> 32) != 0)
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return 0;
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m = findmask(v);
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if(m == nil)
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return 0;
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if(m->s >= 32)
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return 0;
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return 1;
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}
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static int
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@ -618,6 +638,10 @@ aclass(Adr *a)
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}
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if(isbitcon(v))
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return C_BITCON;
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if(isbitcon64(v))
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return C_BITCON64;
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if(isbitcon32(v))
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return C_BITCON32;
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return C_LCON;
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case D_EXTERN:
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@ -716,6 +740,8 @@ oplook(Prog *p)
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if(o->a2 == a2 || c2[o->a2])
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if(c1[o->a1])
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if(c3[o->a3]) {
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if(0)
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print("%P\t-> %d (%d %d %d)\n", p, o->type, o->a1, o->a2, o->a3);
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p->optab = (o-optab)+1;
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return o;
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}
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@ -755,6 +781,11 @@ cmp(int a, int b)
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return 1;
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break;
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case C_BITCON32:
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case C_BITCON64:
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if(b == C_BITCON)
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return 1;
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/* wet floor */
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case C_BITCON:
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if(b == C_ABCON || b == C_MBCON)
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return 1;
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@ -766,7 +797,7 @@ cmp(int a, int b)
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break;
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case C_LCON:
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if(b == C_ZCON || b == C_BITCON || b == C_ADDCON || b == C_ADDCON0 || b == C_ABCON || b == C_MBCON || b == C_MOVCON)
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if(b == C_ZCON || b == C_BITCON || b == C_BITCON32 || b == C_BITCON64 || b == C_ADDCON || b == C_ADDCON0 || b == C_ABCON || b == C_MBCON || b == C_MOVCON)
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return 1;
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break;
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@ -934,20 +965,24 @@ buildop(void)
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break;
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case AAND: /* logical immediate, logical shifted register */
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oprange[AANDS] = t;
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oprange[AEOR] = t;
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oprange[AORR] = t;
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break;
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case AANDW:
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oprange[AANDSW] = t;
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oprange[AANDW] = t;
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oprange[AEOR] = t;
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oprange[AEORW] = t;
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oprange[AORR] = t;
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oprange[AORRW] = t;
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break;
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case ABIC: /* only logical shifted register */
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oprange[ABICS] = t;
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oprange[AEON] = t;
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oprange[AORN] = t;
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break;
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case ABICW:
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oprange[ABICSW] = t;
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oprange[ABICW] = t;
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oprange[AEON] = t;
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oprange[AEONW] = t;
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oprange[AORN] = t;
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oprange[AORNW] = t;
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break;
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case ANEG:
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