2019-03-06 12:10:03 -05:00

5 lines
203 B
C

/* 4 instruction cycles not accessing cache and TLB are needed after
trapa instruction to avoid an SH-4 silicon bug. */
#define NEED_SYSCALL_INST_PAD
#include <sysdeps/unix/sysv/linux/sh/sysdep.h>