549 lines
24 KiB
Zig
549 lines
24 KiB
Zig
const std = @import("std");
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const mem = std.mem;
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const assert = std.debug.assert;
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const ir = @import("ir.zig");
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const Type = @import("type.zig").Type;
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const Value = @import("value.zig").Value;
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const Target = std.Target;
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const Allocator = mem.Allocator;
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pub fn generateSymbol(typed_value: ir.TypedValue, module: ir.Module, code: *std.ArrayList(u8)) !?*ir.ErrorMsg {
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switch (typed_value.ty.zigTypeTag()) {
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.Fn => {
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const module_fn = typed_value.val.cast(Value.Payload.Function).?.func;
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var function = Function{
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.module = &module,
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.mod_fn = module_fn,
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.code = code,
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.inst_table = std.AutoHashMap(*ir.Inst, Function.MCValue).init(code.allocator),
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.err_msg = null,
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};
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defer function.inst_table.deinit();
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for (module_fn.body.instructions) |inst| {
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const new_inst = function.genFuncInst(inst) catch |err| switch (err) {
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error.CodegenFail => {
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assert(function.err_msg != null);
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break;
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},
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else => |e| return e,
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};
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try function.inst_table.putNoClobber(inst, new_inst);
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}
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return function.err_msg;
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},
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else => @panic("TODO implement generateSymbol for non-function decls"),
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}
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}
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const Function = struct {
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module: *const ir.Module,
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mod_fn: *const ir.Module.Fn,
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code: *std.ArrayList(u8),
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inst_table: std.AutoHashMap(*ir.Inst, MCValue),
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err_msg: ?*ir.ErrorMsg,
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const MCValue = union(enum) {
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none,
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unreach,
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/// A pointer-sized integer that fits in a register.
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immediate: u64,
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/// The constant was emitted into the code, at this offset.
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embedded_in_code: usize,
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/// The value is in a target-specific register. The value can
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/// be @intToEnum casted to the respective Reg enum.
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register: usize,
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};
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fn genFuncInst(self: *Function, inst: *ir.Inst) !MCValue {
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switch (inst.tag) {
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.breakpoint => return self.genBreakpoint(inst.src),
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.call => return self.genCall(inst.cast(ir.Inst.Call).?),
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.unreach => return MCValue{ .unreach = {} },
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.constant => unreachable, // excluded from function bodies
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.assembly => return self.genAsm(inst.cast(ir.Inst.Assembly).?),
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.ptrtoint => return self.genPtrToInt(inst.cast(ir.Inst.PtrToInt).?),
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.bitcast => return self.genBitCast(inst.cast(ir.Inst.BitCast).?),
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.ret => return self.genRet(inst.cast(ir.Inst.Ret).?),
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.cmp => return self.genCmp(inst.cast(ir.Inst.Cmp).?),
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.condbr => return self.genCondBr(inst.cast(ir.Inst.CondBr).?),
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.isnull => return self.genIsNull(inst.cast(ir.Inst.IsNull).?),
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.isnonnull => return self.genIsNonNull(inst.cast(ir.Inst.IsNonNull).?),
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}
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}
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fn genBreakpoint(self: *Function, src: usize) !MCValue {
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switch (self.module.target.cpu.arch) {
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.i386, .x86_64 => {
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try self.code.append(0xcc); // int3
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},
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else => return self.fail(src, "TODO implement @breakpoint() for {}", .{self.module.target.cpu.arch}),
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}
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return .unreach;
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}
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fn genCall(self: *Function, inst: *ir.Inst.Call) !MCValue {
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switch (self.module.target.cpu.arch) {
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else => return self.fail(inst.base.src, "TODO implement call for {}", .{self.module.target.cpu.arch}),
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}
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return .unreach;
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}
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fn genRet(self: *Function, inst: *ir.Inst.Ret) !MCValue {
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switch (self.module.target.cpu.arch) {
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.i386, .x86_64 => {
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try self.code.append(0xc3); // ret
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},
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else => return self.fail(inst.base.src, "TODO implement return for {}", .{self.module.target.cpu.arch}),
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}
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return .unreach;
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}
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fn genCmp(self: *Function, inst: *ir.Inst.Cmp) !MCValue {
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switch (self.module.target.cpu.arch) {
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else => return self.fail(inst.base.src, "TODO implement cmp for {}", .{self.module.target.cpu.arch}),
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}
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}
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fn genCondBr(self: *Function, inst: *ir.Inst.CondBr) !MCValue {
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switch (self.module.target.cpu.arch) {
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else => return self.fail(inst.base.src, "TODO implement condbr for {}", .{self.module.target.cpu.arch}),
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}
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}
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fn genIsNull(self: *Function, inst: *ir.Inst.IsNull) !MCValue {
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switch (self.module.target.cpu.arch) {
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else => return self.fail(inst.base.src, "TODO implement isnull for {}", .{self.module.target.cpu.arch}),
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}
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}
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fn genIsNonNull(self: *Function, inst: *ir.Inst.IsNonNull) !MCValue {
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// Here you can specialize this instruction if it makes sense to, otherwise the default
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// will call genIsNull and invert the result.
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switch (self.module.target.cpu.arch) {
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else => return self.fail(inst.base.src, "TODO call genIsNull and invert the result ", .{}),
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}
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}
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fn genRelativeFwdJump(self: *Function, src: usize, amount: u32) !void {
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switch (self.module.target.cpu.arch) {
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.i386, .x86_64 => {
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// TODO x86 treats the operands as signed
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if (amount <= std.math.maxInt(u8)) {
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try self.code.resize(self.code.items.len + 2);
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self.code.items[self.code.items.len - 2] = 0xeb;
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self.code.items[self.code.items.len - 1] = @intCast(u8, amount);
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} else {
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try self.code.resize(self.code.items.len + 5);
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self.code.items[self.code.items.len - 5] = 0xe9; // jmp rel32
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const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4];
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mem.writeIntLittle(u32, imm_ptr, amount);
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}
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},
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else => return self.fail(src, "TODO implement relative forward jump for {}", .{self.module.target.cpu.arch}),
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}
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}
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fn genAsm(self: *Function, inst: *ir.Inst.Assembly) !MCValue {
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// TODO convert to inline function
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switch (self.module.target.cpu.arch) {
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.arm => return self.genAsmArch(.arm, inst),
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.armeb => return self.genAsmArch(.armeb, inst),
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.aarch64 => return self.genAsmArch(.aarch64, inst),
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.aarch64_be => return self.genAsmArch(.aarch64_be, inst),
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.aarch64_32 => return self.genAsmArch(.aarch64_32, inst),
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.arc => return self.genAsmArch(.arc, inst),
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.avr => return self.genAsmArch(.avr, inst),
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.bpfel => return self.genAsmArch(.bpfel, inst),
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.bpfeb => return self.genAsmArch(.bpfeb, inst),
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.hexagon => return self.genAsmArch(.hexagon, inst),
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.mips => return self.genAsmArch(.mips, inst),
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.mipsel => return self.genAsmArch(.mipsel, inst),
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.mips64 => return self.genAsmArch(.mips64, inst),
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.mips64el => return self.genAsmArch(.mips64el, inst),
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.msp430 => return self.genAsmArch(.msp430, inst),
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.powerpc => return self.genAsmArch(.powerpc, inst),
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.powerpc64 => return self.genAsmArch(.powerpc64, inst),
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.powerpc64le => return self.genAsmArch(.powerpc64le, inst),
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.r600 => return self.genAsmArch(.r600, inst),
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.amdgcn => return self.genAsmArch(.amdgcn, inst),
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.riscv32 => return self.genAsmArch(.riscv32, inst),
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.riscv64 => return self.genAsmArch(.riscv64, inst),
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.sparc => return self.genAsmArch(.sparc, inst),
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.sparcv9 => return self.genAsmArch(.sparcv9, inst),
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.sparcel => return self.genAsmArch(.sparcel, inst),
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.s390x => return self.genAsmArch(.s390x, inst),
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.tce => return self.genAsmArch(.tce, inst),
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.tcele => return self.genAsmArch(.tcele, inst),
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.thumb => return self.genAsmArch(.thumb, inst),
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.thumbeb => return self.genAsmArch(.thumbeb, inst),
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.i386 => return self.genAsmArch(.i386, inst),
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.x86_64 => return self.genAsmArch(.x86_64, inst),
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.xcore => return self.genAsmArch(.xcore, inst),
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.nvptx => return self.genAsmArch(.nvptx, inst),
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.nvptx64 => return self.genAsmArch(.nvptx64, inst),
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.le32 => return self.genAsmArch(.le32, inst),
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.le64 => return self.genAsmArch(.le64, inst),
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.amdil => return self.genAsmArch(.amdil, inst),
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.amdil64 => return self.genAsmArch(.amdil64, inst),
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.hsail => return self.genAsmArch(.hsail, inst),
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.hsail64 => return self.genAsmArch(.hsail64, inst),
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.spir => return self.genAsmArch(.spir, inst),
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.spir64 => return self.genAsmArch(.spir64, inst),
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.kalimba => return self.genAsmArch(.kalimba, inst),
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.shave => return self.genAsmArch(.shave, inst),
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.lanai => return self.genAsmArch(.lanai, inst),
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.wasm32 => return self.genAsmArch(.wasm32, inst),
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.wasm64 => return self.genAsmArch(.wasm64, inst),
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.renderscript32 => return self.genAsmArch(.renderscript32, inst),
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.renderscript64 => return self.genAsmArch(.renderscript64, inst),
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.ve => return self.genAsmArch(.ve, inst),
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}
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}
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fn genAsmArch(self: *Function, comptime arch: Target.Cpu.Arch, inst: *ir.Inst.Assembly) !MCValue {
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if (arch != .x86_64 and arch != .i386) {
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return self.fail(inst.base.src, "TODO implement inline asm support for more architectures", .{});
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}
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for (inst.args.inputs) |input, i| {
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if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm input constraint: '{}'", .{input});
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}
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const reg_name = input[1 .. input.len - 1];
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const reg = parseRegName(arch, reg_name) orelse
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return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name});
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const arg = try self.resolveInst(inst.args.args[i]);
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try self.genSetReg(inst.base.src, arch, reg, arg);
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}
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if (mem.eql(u8, inst.args.asm_source, "syscall")) {
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try self.code.appendSlice(&[_]u8{ 0x0f, 0x05 });
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} else {
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return self.fail(inst.base.src, "TODO implement support for more x86 assembly instructions", .{});
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}
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if (inst.args.output) |output| {
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if (output.len < 4 or output[0] != '=' or output[1] != '{' or output[output.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm output constraint: '{}'", .{output});
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}
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const reg_name = output[2 .. output.len - 1];
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const reg = parseRegName(arch, reg_name) orelse
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return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name});
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return MCValue{ .register = @enumToInt(reg) };
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} else {
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return MCValue.none;
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}
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}
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fn genSetReg(self: *Function, src: usize, comptime arch: Target.Cpu.Arch, reg: Reg(arch), mcv: MCValue) !void {
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switch (arch) {
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.x86_64 => switch (reg) {
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.rax => switch (mcv) {
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.none, .unreach => unreachable,
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.immediate => |x| {
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// Setting the eax register zeroes the upper part of rax, so if the number is small
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// enough, that is preferable.
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// Best case: zero
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// 31 c0 xor eax,eax
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if (x == 0) {
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return self.code.appendSlice(&[_]u8{ 0x31, 0xc0 });
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}
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// Next best case: set eax with 4 bytes
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// b8 04 03 02 01 mov eax,0x01020304
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if (x <= std.math.maxInt(u32)) {
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try self.code.resize(self.code.items.len + 5);
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self.code.items[self.code.items.len - 5] = 0xb8;
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const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4];
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mem.writeIntLittle(u32, imm_ptr, @intCast(u32, x));
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return;
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}
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// Worst case: set rax with 8 bytes
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// 48 b8 08 07 06 05 04 03 02 01 movabs rax,0x0102030405060708
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try self.code.resize(self.code.items.len + 10);
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self.code.items[self.code.items.len - 10] = 0x48;
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self.code.items[self.code.items.len - 9] = 0xb8;
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const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8];
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mem.writeIntLittle(u64, imm_ptr, x);
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return;
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},
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.embedded_in_code => return self.fail(src, "TODO implement x86_64 genSetReg %rax = embedded_in_code", .{}),
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.register => return self.fail(src, "TODO implement x86_64 genSetReg %rax = register", .{}),
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},
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.rdx => switch (mcv) {
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.none, .unreach => unreachable,
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.immediate => |x| {
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// Setting the edx register zeroes the upper part of rdx, so if the number is small
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// enough, that is preferable.
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// Best case: zero
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// 31 d2 xor edx,edx
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if (x == 0) {
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return self.code.appendSlice(&[_]u8{ 0x31, 0xd2 });
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}
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// Next best case: set edx with 4 bytes
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// ba 04 03 02 01 mov edx,0x1020304
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if (x <= std.math.maxInt(u32)) {
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try self.code.resize(self.code.items.len + 5);
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self.code.items[self.code.items.len - 5] = 0xba;
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const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4];
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mem.writeIntLittle(u32, imm_ptr, @intCast(u32, x));
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return;
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}
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// Worst case: set rdx with 8 bytes
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// 48 ba 08 07 06 05 04 03 02 01 movabs rdx,0x0102030405060708
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try self.code.resize(self.code.items.len + 10);
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self.code.items[self.code.items.len - 10] = 0x48;
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self.code.items[self.code.items.len - 9] = 0xba;
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const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8];
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mem.writeIntLittle(u64, imm_ptr, x);
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return;
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},
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.embedded_in_code => return self.fail(src, "TODO implement x86_64 genSetReg %rdx = embedded_in_code", .{}),
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.register => return self.fail(src, "TODO implement x86_64 genSetReg %rdx = register", .{}),
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},
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.rdi => switch (mcv) {
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.none, .unreach => unreachable,
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.immediate => |x| {
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// Setting the edi register zeroes the upper part of rdi, so if the number is small
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// enough, that is preferable.
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// Best case: zero
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// 31 ff xor edi,edi
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if (x == 0) {
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return self.code.appendSlice(&[_]u8{ 0x31, 0xff });
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}
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// Next best case: set edi with 4 bytes
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// bf 04 03 02 01 mov edi,0x1020304
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if (x <= std.math.maxInt(u32)) {
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try self.code.resize(self.code.items.len + 5);
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self.code.items[self.code.items.len - 5] = 0xbf;
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const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4];
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mem.writeIntLittle(u32, imm_ptr, @intCast(u32, x));
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return;
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}
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// Worst case: set rdi with 8 bytes
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// 48 bf 08 07 06 05 04 03 02 01 movabs rax,0x0102030405060708
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try self.code.resize(self.code.items.len + 10);
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self.code.items[self.code.items.len - 10] = 0x48;
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self.code.items[self.code.items.len - 9] = 0xbf;
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const imm_ptr = self.code.items[self.code.items.len - 8 ..][0..8];
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mem.writeIntLittle(u64, imm_ptr, x);
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return;
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},
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.embedded_in_code => return self.fail(src, "TODO implement x86_64 genSetReg %rdi = embedded_in_code", .{}),
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.register => return self.fail(src, "TODO implement x86_64 genSetReg %rdi = register", .{}),
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},
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.rsi => switch (mcv) {
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.none, .unreach => unreachable,
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.immediate => return self.fail(src, "TODO implement x86_64 genSetReg %rsi = immediate", .{}),
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.embedded_in_code => |code_offset| {
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// Examples:
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// lea rsi, [rip + 0x01020304]
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// lea rsi, [rip - 7]
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// f: 48 8d 35 04 03 02 01 lea rsi,[rip+0x1020304] # 102031a <_start+0x102031a>
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// 16: 48 8d 35 f9 ff ff ff lea rsi,[rip+0xfffffffffffffff9] # 16 <_start+0x16>
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//
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// We need the offset from RIP in a signed i32 twos complement.
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// The instruction is 7 bytes long and RIP points to the next instruction.
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try self.code.resize(self.code.items.len + 7);
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const rip = self.code.items.len;
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const big_offset = @intCast(i64, code_offset) - @intCast(i64, rip);
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const offset = @intCast(i32, big_offset);
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self.code.items[self.code.items.len - 7] = 0x48;
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self.code.items[self.code.items.len - 6] = 0x8d;
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self.code.items[self.code.items.len - 5] = 0x35;
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const imm_ptr = self.code.items[self.code.items.len - 4 ..][0..4];
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mem.writeIntLittle(i32, imm_ptr, offset);
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return;
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},
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.register => return self.fail(src, "TODO implement x86_64 genSetReg %rsi = register", .{}),
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},
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else => return self.fail(src, "TODO implement genSetReg for x86_64 '{}'", .{@tagName(reg)}),
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},
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else => return self.fail(src, "TODO implement genSetReg for more architectures", .{}),
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}
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}
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fn genPtrToInt(self: *Function, inst: *ir.Inst.PtrToInt) !MCValue {
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// no-op
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return self.resolveInst(inst.args.ptr);
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}
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fn genBitCast(self: *Function, inst: *ir.Inst.BitCast) !MCValue {
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const operand = try self.resolveInst(inst.args.operand);
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return operand;
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}
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fn resolveInst(self: *Function, inst: *ir.Inst) !MCValue {
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if (self.inst_table.getValue(inst)) |mcv| {
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return mcv;
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}
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if (inst.cast(ir.Inst.Constant)) |const_inst| {
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const mcvalue = try self.genTypedValue(inst.src, .{ .ty = inst.ty, .val = const_inst.val });
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try self.inst_table.putNoClobber(inst, mcvalue);
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return mcvalue;
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|
} else {
|
|
return self.inst_table.getValue(inst).?;
|
|
}
|
|
}
|
|
|
|
fn genTypedValue(self: *Function, src: usize, typed_value: ir.TypedValue) !MCValue {
|
|
switch (typed_value.ty.zigTypeTag()) {
|
|
.Pointer => {
|
|
const ptr_elem_type = typed_value.ty.elemType();
|
|
switch (ptr_elem_type.zigTypeTag()) {
|
|
.Array => {
|
|
// TODO more checks to make sure this can be emitted as a string literal
|
|
const bytes = try typed_value.val.toAllocatedBytes(self.code.allocator);
|
|
defer self.code.allocator.free(bytes);
|
|
const smaller_len = std.math.cast(u32, bytes.len) catch
|
|
return self.fail(src, "TODO handle a larger string constant", .{});
|
|
|
|
// Emit the string literal directly into the code; jump over it.
|
|
try self.genRelativeFwdJump(src, smaller_len);
|
|
const offset = self.code.items.len;
|
|
try self.code.appendSlice(bytes);
|
|
return MCValue{ .embedded_in_code = offset };
|
|
},
|
|
else => |t| return self.fail(src, "TODO implement emitTypedValue for pointer to '{}'", .{@tagName(t)}),
|
|
}
|
|
},
|
|
.Int => {
|
|
const info = typed_value.ty.intInfo(self.module.target);
|
|
const ptr_bits = self.module.target.cpu.arch.ptrBitWidth();
|
|
if (info.bits > ptr_bits or info.signed) {
|
|
return self.fail(src, "TODO const int bigger than ptr and signed int", .{});
|
|
}
|
|
return MCValue{ .immediate = typed_value.val.toUnsignedInt() };
|
|
},
|
|
.ComptimeInt => unreachable, // semantic analysis prevents this
|
|
.ComptimeFloat => unreachable, // semantic analysis prevents this
|
|
else => return self.fail(src, "TODO implement const of type '{}'", .{typed_value.ty}),
|
|
}
|
|
}
|
|
|
|
fn fail(self: *Function, src: usize, comptime format: []const u8, args: var) error{ CodegenFail, OutOfMemory } {
|
|
@setCold(true);
|
|
assert(self.err_msg == null);
|
|
self.err_msg = try ir.ErrorMsg.create(self.code.allocator, src, format, args);
|
|
return error.CodegenFail;
|
|
}
|
|
};
|
|
|
|
fn Reg(comptime arch: Target.Cpu.Arch) type {
|
|
return switch (arch) {
|
|
.i386 => enum {
|
|
eax,
|
|
ebx,
|
|
ecx,
|
|
edx,
|
|
ebp,
|
|
esp,
|
|
esi,
|
|
edi,
|
|
|
|
ax,
|
|
bx,
|
|
cx,
|
|
dx,
|
|
bp,
|
|
sp,
|
|
si,
|
|
di,
|
|
|
|
ah,
|
|
bh,
|
|
ch,
|
|
dh,
|
|
|
|
al,
|
|
bl,
|
|
cl,
|
|
dl,
|
|
},
|
|
.x86_64 => enum {
|
|
rax,
|
|
rbx,
|
|
rcx,
|
|
rdx,
|
|
rbp,
|
|
rsp,
|
|
rsi,
|
|
rdi,
|
|
r8,
|
|
r9,
|
|
r10,
|
|
r11,
|
|
r12,
|
|
r13,
|
|
r14,
|
|
r15,
|
|
|
|
eax,
|
|
ebx,
|
|
ecx,
|
|
edx,
|
|
ebp,
|
|
esp,
|
|
esi,
|
|
edi,
|
|
r8d,
|
|
r9d,
|
|
r10d,
|
|
r11d,
|
|
r12d,
|
|
r13d,
|
|
r14d,
|
|
r15d,
|
|
|
|
ax,
|
|
bx,
|
|
cx,
|
|
dx,
|
|
bp,
|
|
sp,
|
|
si,
|
|
di,
|
|
r8w,
|
|
r9w,
|
|
r10w,
|
|
r11w,
|
|
r12w,
|
|
r13w,
|
|
r14w,
|
|
r15w,
|
|
|
|
ah,
|
|
bh,
|
|
ch,
|
|
dh,
|
|
bph,
|
|
sph,
|
|
sih,
|
|
dih,
|
|
|
|
al,
|
|
bl,
|
|
cl,
|
|
dl,
|
|
bpl,
|
|
spl,
|
|
sil,
|
|
dil,
|
|
r8b,
|
|
r9b,
|
|
r10b,
|
|
r11b,
|
|
r12b,
|
|
r13b,
|
|
r14b,
|
|
r15b,
|
|
},
|
|
else => @compileError("TODO add more register enums"),
|
|
};
|
|
}
|
|
|
|
fn parseRegName(comptime arch: Target.Cpu.Arch, name: []const u8) ?Reg(arch) {
|
|
return std.meta.stringToEnum(Reg(arch), name);
|
|
}
|