Intel keeps changing the latency & throughput of the aes* and clmul instructions every time they release a new model. Adjust `optimal_parallel_blocks` accordingly, keeping 8 as a safe default for unknown data.
Intel keeps changing the latency & throughput of the aes* and clmul instructions every time they release a new model. Adjust `optimal_parallel_blocks` accordingly, keeping 8 as a safe default for unknown data.