2861 lines
73 KiB
Zig
2861 lines
73 KiB
Zig
const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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pub const Feature = enum {
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@"3dnow",
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@"3dnowa",
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@"64bit",
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adx,
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aes,
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avx,
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avx2,
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avx512bf16,
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avx512bitalg,
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avx512bw,
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avx512cd,
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avx512dq,
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avx512er,
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avx512f,
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avx512ifma,
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avx512pf,
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avx512vbmi,
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avx512vbmi2,
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avx512vl,
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avx512vnni,
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avx512vp2intersect,
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avx512vpopcntdq,
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bmi,
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bmi2,
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branchfusion,
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cldemote,
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clflushopt,
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clwb,
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clzero,
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cmov,
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cx16,
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cx8,
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enqcmd,
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ermsb,
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f16c,
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false_deps_lzcnt_tzcnt,
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false_deps_popcnt,
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fast_11bytenop,
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fast_15bytenop,
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fast_bextr,
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fast_gather,
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fast_hops,
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fast_lzcnt,
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fast_partial_ymm_or_zmm_write,
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fast_scalar_fsqrt,
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fast_scalar_shift_masks,
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fast_shld_rotate,
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fast_variable_shuffle,
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fast_vector_fsqrt,
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fast_vector_shift_masks,
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fma,
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fma4,
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fsgsbase,
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fxsr,
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gfni,
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idivl_to_divb,
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idivq_to_divl,
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invpcid,
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lea_sp,
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lea_uses_ag,
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lwp,
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lzcnt,
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macrofusion,
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merge_to_threeway_branch,
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mmx,
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movbe,
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movdir64b,
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movdiri,
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mpx,
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mwaitx,
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nopl,
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pad_short_functions,
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pclmul,
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pconfig,
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pku,
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popcnt,
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prefer_256_bit,
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prefetchwt1,
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prfchw,
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ptwrite,
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rdpid,
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rdrnd,
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rdseed,
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retpoline,
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retpoline_external_thunk,
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retpoline_indirect_branches,
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retpoline_indirect_calls,
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rtm,
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sahf,
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sgx,
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sha,
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shstk,
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slow_3ops_lea,
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slow_incdec,
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slow_lea,
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slow_pmaddwd,
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slow_pmulld,
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slow_shld,
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slow_two_mem_ops,
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slow_unaligned_mem_16,
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slow_unaligned_mem_32,
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soft_float,
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sse,
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sse_unaligned_mem,
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sse2,
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sse3,
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sse4_1,
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sse4_2,
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sse4a,
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ssse3,
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tbm,
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vaes,
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vpclmulqdq,
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waitpkg,
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wbnoinvd,
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x87,
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xop,
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xsave,
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xsavec,
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xsaveopt,
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xsaves,
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};
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pub usingnamespace CpuFeature.feature_set_fns(Feature);
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pub const all_features = blk: {
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const len = @typeInfo(Feature).Enum.fields.len;
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std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
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var result: [len]CpuFeature = undefined;
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result[@enumToInt(Feature.@"3dnow")] = .{
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.llvm_name = "3dnow",
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.description = "Enable 3DNow! instructions",
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.dependencies = featureSet(&[_]Feature{
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.mmx,
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}),
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};
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result[@enumToInt(Feature.@"3dnowa")] = .{
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.llvm_name = "3dnowa",
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.description = "Enable 3DNow! Athlon instructions",
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.dependencies = featureSet(&[_]Feature{
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.@"3dnow",
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}),
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};
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result[@enumToInt(Feature.@"64bit")] = .{
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.llvm_name = "64bit",
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.description = "Support 64-bit instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.adx)] = .{
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.llvm_name = "adx",
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.description = "Support ADX instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.aes)] = .{
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.llvm_name = "aes",
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.description = "Enable AES instructions",
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.dependencies = featureSet(&[_]Feature{
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.sse2,
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}),
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};
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result[@enumToInt(Feature.avx)] = .{
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.llvm_name = "avx",
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.description = "Enable AVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.sse4_2,
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}),
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};
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result[@enumToInt(Feature.avx2)] = .{
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.llvm_name = "avx2",
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.description = "Enable AVX2 instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx,
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}),
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};
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result[@enumToInt(Feature.avx512bf16)] = .{
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.llvm_name = "avx512bf16",
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.description = "Support bfloat16 floating point",
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.dependencies = featureSet(&[_]Feature{
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.avx512bw,
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}),
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};
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result[@enumToInt(Feature.avx512bitalg)] = .{
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.llvm_name = "avx512bitalg",
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.description = "Enable AVX-512 Bit Algorithms",
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.dependencies = featureSet(&[_]Feature{
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.avx512bw,
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}),
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};
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result[@enumToInt(Feature.avx512bw)] = .{
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.llvm_name = "avx512bw",
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.description = "Enable AVX-512 Byte and Word Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512cd)] = .{
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.llvm_name = "avx512cd",
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.description = "Enable AVX-512 Conflict Detection Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512dq)] = .{
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.llvm_name = "avx512dq",
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.description = "Enable AVX-512 Doubleword and Quadword Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512er)] = .{
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.llvm_name = "avx512er",
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.description = "Enable AVX-512 Exponential and Reciprocal Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512f)] = .{
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.llvm_name = "avx512f",
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.description = "Enable AVX-512 instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx2,
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.f16c,
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.fma,
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}),
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};
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result[@enumToInt(Feature.avx512ifma)] = .{
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.llvm_name = "avx512ifma",
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.description = "Enable AVX-512 Integer Fused Multiple-Add",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512pf)] = .{
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.llvm_name = "avx512pf",
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.description = "Enable AVX-512 PreFetch Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512vbmi)] = .{
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.llvm_name = "avx512vbmi",
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.description = "Enable AVX-512 Vector Byte Manipulation Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512bw,
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}),
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};
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result[@enumToInt(Feature.avx512vbmi2)] = .{
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.llvm_name = "avx512vbmi2",
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.description = "Enable AVX-512 further Vector Byte Manipulation Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512bw,
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}),
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};
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result[@enumToInt(Feature.avx512vl)] = .{
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.llvm_name = "avx512vl",
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.description = "Enable AVX-512 Vector Length eXtensions",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512vnni)] = .{
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.llvm_name = "avx512vnni",
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.description = "Enable AVX-512 Vector Neural Network Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512vp2intersect)] = .{
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.llvm_name = "avx512vp2intersect",
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.description = "Enable AVX-512 vp2intersect",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.avx512vpopcntdq)] = .{
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.llvm_name = "avx512vpopcntdq",
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.description = "Enable AVX-512 Population Count Instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx512f,
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}),
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};
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result[@enumToInt(Feature.bmi)] = .{
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.llvm_name = "bmi",
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.description = "Support BMI instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.bmi2)] = .{
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.llvm_name = "bmi2",
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.description = "Support BMI2 instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.branchfusion)] = .{
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.llvm_name = "branchfusion",
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.description = "CMP/TEST can be fused with conditional branches",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.cldemote)] = .{
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.llvm_name = "cldemote",
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.description = "Enable Cache Demote",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.clflushopt)] = .{
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.llvm_name = "clflushopt",
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.description = "Flush A Cache Line Optimized",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.clwb)] = .{
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.llvm_name = "clwb",
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.description = "Cache Line Write Back",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.clzero)] = .{
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.llvm_name = "clzero",
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.description = "Enable Cache Line Zero",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.cmov)] = .{
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.llvm_name = "cmov",
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.description = "Enable conditional move instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.cx16)] = .{
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.llvm_name = "cx16",
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.description = "64-bit with cmpxchg16b",
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.dependencies = featureSet(&[_]Feature{
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.cx8,
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}),
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};
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result[@enumToInt(Feature.cx8)] = .{
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.llvm_name = "cx8",
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.description = "Support CMPXCHG8B instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.enqcmd)] = .{
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.llvm_name = "enqcmd",
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.description = "Has ENQCMD instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.ermsb)] = .{
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.llvm_name = "ermsb",
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.description = "REP MOVS/STOS are fast",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.f16c)] = .{
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.llvm_name = "f16c",
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.description = "Support 16-bit floating point conversion instructions",
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.dependencies = featureSet(&[_]Feature{
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.avx,
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}),
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};
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result[@enumToInt(Feature.false_deps_lzcnt_tzcnt)] = .{
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.llvm_name = "false-deps-lzcnt-tzcnt",
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.description = "LZCNT/TZCNT have a false dependency on dest register",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.false_deps_popcnt)] = .{
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.llvm_name = "false-deps-popcnt",
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.description = "POPCNT has a false dependency on dest register",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_11bytenop)] = .{
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.llvm_name = "fast-11bytenop",
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.description = "Target can quickly decode up to 11 byte NOPs",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_15bytenop)] = .{
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.llvm_name = "fast-15bytenop",
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.description = "Target can quickly decode up to 15 byte NOPs",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_bextr)] = .{
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.llvm_name = "fast-bextr",
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.description = "Indicates that the BEXTR instruction is implemented as a single uop with good throughput",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_gather)] = .{
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.llvm_name = "fast-gather",
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.description = "Indicates if gather is reasonably fast",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_hops)] = .{
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.llvm_name = "fast-hops",
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.description = "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles",
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.dependencies = featureSet(&[_]Feature{
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.sse3,
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}),
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};
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result[@enumToInt(Feature.fast_lzcnt)] = .{
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.llvm_name = "fast-lzcnt",
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.description = "LZCNT instructions are as fast as most simple integer ops",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_partial_ymm_or_zmm_write)] = .{
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.llvm_name = "fast-partial-ymm-or-zmm-write",
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.description = "Partial writes to YMM/ZMM registers are fast",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_scalar_fsqrt)] = .{
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.llvm_name = "fast-scalar-fsqrt",
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.description = "Scalar SQRT is fast (disable Newton-Raphson)",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_scalar_shift_masks)] = .{
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.llvm_name = "fast-scalar-shift-masks",
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.description = "Prefer a left/right scalar logical shift pair over a shift+and pair",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_shld_rotate)] = .{
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.llvm_name = "fast-shld-rotate",
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.description = "SHLD can be used as a faster rotate",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_variable_shuffle)] = .{
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.llvm_name = "fast-variable-shuffle",
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.description = "Shuffles with variable masks are fast",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_vector_fsqrt)] = .{
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.llvm_name = "fast-vector-fsqrt",
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.description = "Vector SQRT is fast (disable Newton-Raphson)",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fast_vector_shift_masks)] = .{
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.llvm_name = "fast-vector-shift-masks",
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.description = "Prefer a left/right vector logical shift pair over a shift+and pair",
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|
.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fma)] = .{
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.llvm_name = "fma",
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.description = "Enable three-operand fused multiple-add",
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.dependencies = featureSet(&[_]Feature{
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.avx,
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}),
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};
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result[@enumToInt(Feature.fma4)] = .{
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.llvm_name = "fma4",
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.description = "Enable four-operand fused multiple-add",
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|
.dependencies = featureSet(&[_]Feature{
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.avx,
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|
.sse4a,
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|
}),
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|
};
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result[@enumToInt(Feature.fsgsbase)] = .{
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.llvm_name = "fsgsbase",
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.description = "Support FS/GS Base instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fxsr)] = .{
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.llvm_name = "fxsr",
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.description = "Support fxsave/fxrestore instructions",
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|
.dependencies = featureSet(&[_]Feature{}),
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};
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|
result[@enumToInt(Feature.gfni)] = .{
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.llvm_name = "gfni",
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|
.description = "Enable Galois Field Arithmetic Instructions",
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|
.dependencies = featureSet(&[_]Feature{
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|
.sse2,
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|
}),
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|
};
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|
result[@enumToInt(Feature.idivl_to_divb)] = .{
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.llvm_name = "idivl-to-divb",
|
|
.description = "Use 8-bit divide for positive values less than 256",
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|
.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.idivq_to_divl)] = .{
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.llvm_name = "idivq-to-divl",
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|
.description = "Use 32-bit divide for positive values less than 2^32",
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|
.dependencies = featureSet(&[_]Feature{}),
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|
};
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|
result[@enumToInt(Feature.invpcid)] = .{
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.llvm_name = "invpcid",
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|
.description = "Invalidate Process-Context Identifier",
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|
.dependencies = featureSet(&[_]Feature{}),
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|
};
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|
result[@enumToInt(Feature.lea_sp)] = .{
|
|
.llvm_name = "lea-sp",
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|
.description = "Use LEA for adjusting the stack pointer",
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|
.dependencies = featureSet(&[_]Feature{}),
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|
};
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result[@enumToInt(Feature.lea_uses_ag)] = .{
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|
.llvm_name = "lea-uses-ag",
|
|
.description = "LEA instruction needs inputs at AG stage",
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|
.dependencies = featureSet(&[_]Feature{}),
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|
};
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|
result[@enumToInt(Feature.lwp)] = .{
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.llvm_name = "lwp",
|
|
.description = "Enable LWP instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
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|
};
|
|
result[@enumToInt(Feature.lzcnt)] = .{
|
|
.llvm_name = "lzcnt",
|
|
.description = "Support LZCNT instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.macrofusion)] = .{
|
|
.llvm_name = "macrofusion",
|
|
.description = "Various instructions can be fused with conditional branches",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.merge_to_threeway_branch)] = .{
|
|
.llvm_name = "merge-to-threeway-branch",
|
|
.description = "Merge branches to a three-way conditional branch",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.mmx)] = .{
|
|
.llvm_name = "mmx",
|
|
.description = "Enable MMX instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.movbe)] = .{
|
|
.llvm_name = "movbe",
|
|
.description = "Support MOVBE instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.movdir64b)] = .{
|
|
.llvm_name = "movdir64b",
|
|
.description = "Support movdir64b instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.movdiri)] = .{
|
|
.llvm_name = "movdiri",
|
|
.description = "Support movdiri instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.mpx)] = .{
|
|
.llvm_name = "mpx",
|
|
.description = "Support MPX instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.mwaitx)] = .{
|
|
.llvm_name = "mwaitx",
|
|
.description = "Enable MONITORX/MWAITX timer functionality",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.nopl)] = .{
|
|
.llvm_name = "nopl",
|
|
.description = "Enable NOPL instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.pad_short_functions)] = .{
|
|
.llvm_name = "pad-short-functions",
|
|
.description = "Pad short functions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.pclmul)] = .{
|
|
.llvm_name = "pclmul",
|
|
.description = "Enable packed carry-less multiplication instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.sse2,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.pconfig)] = .{
|
|
.llvm_name = "pconfig",
|
|
.description = "platform configuration instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.pku)] = .{
|
|
.llvm_name = "pku",
|
|
.description = "Enable protection keys",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.popcnt)] = .{
|
|
.llvm_name = "popcnt",
|
|
.description = "Support POPCNT instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.prefer_256_bit)] = .{
|
|
.llvm_name = "prefer-256-bit",
|
|
.description = "Prefer 256-bit AVX instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.prefetchwt1)] = .{
|
|
.llvm_name = "prefetchwt1",
|
|
.description = "Prefetch with Intent to Write and T1 Hint",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.prfchw)] = .{
|
|
.llvm_name = "prfchw",
|
|
.description = "Support PRFCHW instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.ptwrite)] = .{
|
|
.llvm_name = "ptwrite",
|
|
.description = "Support ptwrite instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.rdpid)] = .{
|
|
.llvm_name = "rdpid",
|
|
.description = "Support RDPID instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.rdrnd)] = .{
|
|
.llvm_name = "rdrnd",
|
|
.description = "Support RDRAND instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.rdseed)] = .{
|
|
.llvm_name = "rdseed",
|
|
.description = "Support RDSEED instruction",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.retpoline)] = .{
|
|
.llvm_name = "retpoline",
|
|
.description = "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.retpoline_indirect_branches,
|
|
.retpoline_indirect_calls,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.retpoline_external_thunk)] = .{
|
|
.llvm_name = "retpoline-external-thunk",
|
|
.description = "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.retpoline_indirect_calls,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.retpoline_indirect_branches)] = .{
|
|
.llvm_name = "retpoline-indirect-branches",
|
|
.description = "Remove speculation of indirect branches from the generated code",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.retpoline_indirect_calls)] = .{
|
|
.llvm_name = "retpoline-indirect-calls",
|
|
.description = "Remove speculation of indirect calls from the generated code",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.rtm)] = .{
|
|
.llvm_name = "rtm",
|
|
.description = "Support RTM instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.sahf)] = .{
|
|
.llvm_name = "sahf",
|
|
.description = "Support LAHF and SAHF instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.sgx)] = .{
|
|
.llvm_name = "sgx",
|
|
.description = "Enable Software Guard Extensions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.sha)] = .{
|
|
.llvm_name = "sha",
|
|
.description = "Enable SHA instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.sse2,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.shstk)] = .{
|
|
.llvm_name = "shstk",
|
|
.description = "Support CET Shadow-Stack instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_3ops_lea)] = .{
|
|
.llvm_name = "slow-3ops-lea",
|
|
.description = "LEA instruction with 3 ops or certain registers is slow",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_incdec)] = .{
|
|
.llvm_name = "slow-incdec",
|
|
.description = "INC and DEC instructions are slower than ADD and SUB",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_lea)] = .{
|
|
.llvm_name = "slow-lea",
|
|
.description = "LEA instruction with certain arguments is slow",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_pmaddwd)] = .{
|
|
.llvm_name = "slow-pmaddwd",
|
|
.description = "PMADDWD is slower than PMULLD",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_pmulld)] = .{
|
|
.llvm_name = "slow-pmulld",
|
|
.description = "PMULLD instruction is slow",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_shld)] = .{
|
|
.llvm_name = "slow-shld",
|
|
.description = "SHLD instruction is slow",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_two_mem_ops)] = .{
|
|
.llvm_name = "slow-two-mem-ops",
|
|
.description = "Two memory operand instructions are slow",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_unaligned_mem_16)] = .{
|
|
.llvm_name = "slow-unaligned-mem-16",
|
|
.description = "Slow unaligned 16-byte memory access",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.slow_unaligned_mem_32)] = .{
|
|
.llvm_name = "slow-unaligned-mem-32",
|
|
.description = "Slow unaligned 32-byte memory access",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.soft_float)] = .{
|
|
.llvm_name = "soft-float",
|
|
.description = "Use software floating point features",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.sse)] = .{
|
|
.llvm_name = "sse",
|
|
.description = "Enable SSE instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.sse_unaligned_mem)] = .{
|
|
.llvm_name = "sse-unaligned-mem",
|
|
.description = "Allow unaligned memory operands with SSE instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.sse2)] = .{
|
|
.llvm_name = "sse2",
|
|
.description = "Enable SSE2 instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.sse,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.sse3)] = .{
|
|
.llvm_name = "sse3",
|
|
.description = "Enable SSE3 instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.sse2,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.sse4_1)] = .{
|
|
.llvm_name = "sse4.1",
|
|
.description = "Enable SSE 4.1 instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.ssse3,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.sse4_2)] = .{
|
|
.llvm_name = "sse4.2",
|
|
.description = "Enable SSE 4.2 instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.sse4_1,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.sse4a)] = .{
|
|
.llvm_name = "sse4a",
|
|
.description = "Support SSE 4a instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.sse3,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.ssse3)] = .{
|
|
.llvm_name = "ssse3",
|
|
.description = "Enable SSSE3 instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.sse3,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.tbm)] = .{
|
|
.llvm_name = "tbm",
|
|
.description = "Enable TBM instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.vaes)] = .{
|
|
.llvm_name = "vaes",
|
|
.description = "Promote selected AES instructions to AVX512/AVX registers",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.aes,
|
|
.avx,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.vpclmulqdq)] = .{
|
|
.llvm_name = "vpclmulqdq",
|
|
.description = "Enable vpclmulqdq instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.avx,
|
|
.pclmul,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.waitpkg)] = .{
|
|
.llvm_name = "waitpkg",
|
|
.description = "Wait and pause enhancements",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.wbnoinvd)] = .{
|
|
.llvm_name = "wbnoinvd",
|
|
.description = "Write Back No Invalidate",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.x87)] = .{
|
|
.llvm_name = "x87",
|
|
.description = "Enable X87 float instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.xop)] = .{
|
|
.llvm_name = "xop",
|
|
.description = "Enable XOP instructions",
|
|
.dependencies = featureSet(&[_]Feature{
|
|
.fma4,
|
|
}),
|
|
};
|
|
result[@enumToInt(Feature.xsave)] = .{
|
|
.llvm_name = "xsave",
|
|
.description = "Support xsave instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.xsavec)] = .{
|
|
.llvm_name = "xsavec",
|
|
.description = "Support xsavec instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.xsaveopt)] = .{
|
|
.llvm_name = "xsaveopt",
|
|
.description = "Support xsaveopt instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
result[@enumToInt(Feature.xsaves)] = .{
|
|
.llvm_name = "xsaves",
|
|
.description = "Support xsaves instructions",
|
|
.dependencies = featureSet(&[_]Feature{}),
|
|
};
|
|
const ti = @typeInfo(Feature);
|
|
for (result) |*elem, i| {
|
|
elem.index = i;
|
|
elem.name = ti.Enum.fields[i].name;
|
|
}
|
|
break :blk result;
|
|
};
|
|
|
|
pub const cpu = struct {
|
|
pub const amdfam10 = CpuModel{
|
|
.name = "amdfam10",
|
|
.llvm_name = "amdfam10",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.lzcnt,
|
|
.nopl,
|
|
.popcnt,
|
|
.sahf,
|
|
.slow_shld,
|
|
.sse4a,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const athlon = CpuModel{
|
|
.name = "athlon",
|
|
.llvm_name = "athlon",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.cmov,
|
|
.cx8,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const athlon_4 = CpuModel{
|
|
.name = "athlon_4",
|
|
.llvm_name = "athlon-4",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const athlon_fx = CpuModel{
|
|
.name = "athlon_fx",
|
|
.llvm_name = "athlon-fx",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const athlon_mp = CpuModel{
|
|
.name = "athlon_mp",
|
|
.llvm_name = "athlon-mp",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const athlon_tbird = CpuModel{
|
|
.name = "athlon_tbird",
|
|
.llvm_name = "athlon-tbird",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.cmov,
|
|
.cx8,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const athlon_xp = CpuModel{
|
|
.name = "athlon_xp",
|
|
.llvm_name = "athlon-xp",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const athlon64 = CpuModel{
|
|
.name = "athlon64",
|
|
.llvm_name = "athlon64",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const athlon64_sse3 = CpuModel{
|
|
.name = "athlon64_sse3",
|
|
.llvm_name = "athlon64-sse3",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const atom = CpuModel{
|
|
.name = "atom",
|
|
.llvm_name = "atom",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fxsr,
|
|
.idivl_to_divb,
|
|
.idivq_to_divl,
|
|
.lea_sp,
|
|
.lea_uses_ag,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pad_short_functions,
|
|
.sahf,
|
|
.slow_two_mem_ops,
|
|
.slow_unaligned_mem_16,
|
|
.ssse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const barcelona = CpuModel{
|
|
.name = "barcelona",
|
|
.llvm_name = "barcelona",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.lzcnt,
|
|
.nopl,
|
|
.popcnt,
|
|
.sahf,
|
|
.slow_shld,
|
|
.sse4a,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const bdver1 = CpuModel{
|
|
.name = "bdver1",
|
|
.llvm_name = "bdver1",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.aes,
|
|
.branchfusion,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fast_11bytenop,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.lwp,
|
|
.lzcnt,
|
|
.mmx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.sahf,
|
|
.slow_shld,
|
|
.x87,
|
|
.xop,
|
|
.xsave,
|
|
}),
|
|
};
|
|
pub const bdver2 = CpuModel{
|
|
.name = "bdver2",
|
|
.llvm_name = "bdver2",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.aes,
|
|
.bmi,
|
|
.branchfusion,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.f16c,
|
|
.fast_11bytenop,
|
|
.fast_bextr,
|
|
.fast_scalar_shift_masks,
|
|
.fma,
|
|
.fxsr,
|
|
.lwp,
|
|
.lzcnt,
|
|
.mmx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.sahf,
|
|
.slow_shld,
|
|
.tbm,
|
|
.x87,
|
|
.xop,
|
|
.xsave,
|
|
}),
|
|
};
|
|
pub const bdver3 = CpuModel{
|
|
.name = "bdver3",
|
|
.llvm_name = "bdver3",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.aes,
|
|
.bmi,
|
|
.branchfusion,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.f16c,
|
|
.fast_11bytenop,
|
|
.fast_bextr,
|
|
.fast_scalar_shift_masks,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.lwp,
|
|
.lzcnt,
|
|
.mmx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.sahf,
|
|
.slow_shld,
|
|
.tbm,
|
|
.x87,
|
|
.xop,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const bdver4 = CpuModel{
|
|
.name = "bdver4",
|
|
.llvm_name = "bdver4",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.aes,
|
|
.avx2,
|
|
.bmi,
|
|
.bmi2,
|
|
.branchfusion,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.f16c,
|
|
.fast_11bytenop,
|
|
.fast_bextr,
|
|
.fast_scalar_shift_masks,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.lwp,
|
|
.lzcnt,
|
|
.mmx,
|
|
.mwaitx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.sahf,
|
|
.slow_shld,
|
|
.tbm,
|
|
.x87,
|
|
.xop,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const bonnell = CpuModel{
|
|
.name = "bonnell",
|
|
.llvm_name = "bonnell",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fxsr,
|
|
.idivl_to_divb,
|
|
.idivq_to_divl,
|
|
.lea_sp,
|
|
.lea_uses_ag,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pad_short_functions,
|
|
.sahf,
|
|
.slow_two_mem_ops,
|
|
.slow_unaligned_mem_16,
|
|
.ssse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const broadwell = CpuModel{
|
|
.name = "broadwell",
|
|
.llvm_name = "broadwell",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.avx,
|
|
.avx2,
|
|
.bmi,
|
|
.bmi2,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.false_deps_lzcnt_tzcnt,
|
|
.false_deps_popcnt,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const btver1 = CpuModel{
|
|
.name = "btver1",
|
|
.llvm_name = "btver1",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fast_15bytenop,
|
|
.fast_scalar_shift_masks,
|
|
.fast_vector_shift_masks,
|
|
.fxsr,
|
|
.lzcnt,
|
|
.mmx,
|
|
.nopl,
|
|
.popcnt,
|
|
.prfchw,
|
|
.sahf,
|
|
.slow_shld,
|
|
.sse4a,
|
|
.ssse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const btver2 = CpuModel{
|
|
.name = "btver2",
|
|
.llvm_name = "btver2",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.aes,
|
|
.avx,
|
|
.bmi,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.f16c,
|
|
.fast_15bytenop,
|
|
.fast_bextr,
|
|
.fast_hops,
|
|
.fast_lzcnt,
|
|
.fast_partial_ymm_or_zmm_write,
|
|
.fast_scalar_shift_masks,
|
|
.fast_vector_shift_masks,
|
|
.fxsr,
|
|
.lzcnt,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.sahf,
|
|
.slow_shld,
|
|
.sse4a,
|
|
.ssse3,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const c3 = CpuModel{
|
|
.name = "c3",
|
|
.llvm_name = "c3",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnow",
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const c3_2 = CpuModel{
|
|
.name = "c3_2",
|
|
.llvm_name = "c3-2",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.slow_unaligned_mem_16,
|
|
.sse,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const cannonlake = CpuModel{
|
|
.name = "cannonlake",
|
|
.llvm_name = "cannonlake",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx,
|
|
.avx2,
|
|
.avx512bw,
|
|
.avx512cd,
|
|
.avx512dq,
|
|
.avx512f,
|
|
.avx512ifma,
|
|
.avx512vbmi,
|
|
.avx512vl,
|
|
.bmi,
|
|
.bmi2,
|
|
.clflushopt,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.fast_gather,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fast_vector_fsqrt,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.pku,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sgx,
|
|
.sha,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const cascadelake = CpuModel{
|
|
.name = "cascadelake",
|
|
.llvm_name = "cascadelake",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx,
|
|
.avx2,
|
|
.avx512bw,
|
|
.avx512cd,
|
|
.avx512dq,
|
|
.avx512f,
|
|
.avx512vl,
|
|
.avx512vnni,
|
|
.bmi,
|
|
.bmi2,
|
|
.clflushopt,
|
|
.clwb,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.false_deps_popcnt,
|
|
.fast_gather,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fast_vector_fsqrt,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.pku,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const cooperlake = CpuModel{
|
|
.name = "cooperlake",
|
|
.llvm_name = "cooperlake",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx,
|
|
.avx2,
|
|
.avx512bf16,
|
|
.avx512bw,
|
|
.avx512cd,
|
|
.avx512dq,
|
|
.avx512f,
|
|
.avx512vl,
|
|
.avx512vnni,
|
|
.bmi,
|
|
.bmi2,
|
|
.clflushopt,
|
|
.clwb,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.false_deps_popcnt,
|
|
.fast_gather,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fast_vector_fsqrt,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.pku,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const core_avx_i = CpuModel{
|
|
.name = "core_avx_i",
|
|
.llvm_name = "core-avx-i",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.avx,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.f16c,
|
|
.false_deps_popcnt,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.rdrnd,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.slow_unaligned_mem_32,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const core_avx2 = CpuModel{
|
|
.name = "core_avx2",
|
|
.llvm_name = "core-avx2",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.avx,
|
|
.avx2,
|
|
.bmi,
|
|
.bmi2,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.false_deps_lzcnt_tzcnt,
|
|
.false_deps_popcnt,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.rdrnd,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const core2 = CpuModel{
|
|
.name = "core2",
|
|
.llvm_name = "core2",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fxsr,
|
|
.macrofusion,
|
|
.mmx,
|
|
.nopl,
|
|
.sahf,
|
|
.slow_unaligned_mem_16,
|
|
.ssse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const corei7 = CpuModel{
|
|
.name = "corei7",
|
|
.llvm_name = "corei7",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fxsr,
|
|
.macrofusion,
|
|
.mmx,
|
|
.nopl,
|
|
.popcnt,
|
|
.sahf,
|
|
.sse4_2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const corei7_avx = CpuModel{
|
|
.name = "corei7_avx",
|
|
.llvm_name = "corei7-avx",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.avx,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.false_deps_popcnt,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.slow_unaligned_mem_32,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const generic = CpuModel{
|
|
.name = "generic",
|
|
.llvm_name = "generic",
|
|
.features = featureSet(&[_]Feature{
|
|
.cx8,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const geode = CpuModel{
|
|
.name = "geode",
|
|
.llvm_name = "geode",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.cx8,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const goldmont = CpuModel{
|
|
.name = "goldmont",
|
|
.llvm_name = "goldmont",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.aes,
|
|
.clflushopt,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.false_deps_popcnt,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sha,
|
|
.slow_incdec,
|
|
.slow_lea,
|
|
.slow_two_mem_ops,
|
|
.sse4_2,
|
|
.ssse3,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const goldmont_plus = CpuModel{
|
|
.name = "goldmont_plus",
|
|
.llvm_name = "goldmont-plus",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.aes,
|
|
.clflushopt,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.ptwrite,
|
|
.rdpid,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sgx,
|
|
.sha,
|
|
.slow_incdec,
|
|
.slow_lea,
|
|
.slow_two_mem_ops,
|
|
.sse4_2,
|
|
.ssse3,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const haswell = CpuModel{
|
|
.name = "haswell",
|
|
.llvm_name = "haswell",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.avx,
|
|
.avx2,
|
|
.bmi,
|
|
.bmi2,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.false_deps_lzcnt_tzcnt,
|
|
.false_deps_popcnt,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.rdrnd,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const _i386 = CpuModel{
|
|
.name = "_i386",
|
|
.llvm_name = "i386",
|
|
.features = featureSet(&[_]Feature{
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const _i486 = CpuModel{
|
|
.name = "_i486",
|
|
.llvm_name = "i486",
|
|
.features = featureSet(&[_]Feature{
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const _i586 = CpuModel{
|
|
.name = "_i586",
|
|
.llvm_name = "i586",
|
|
.features = featureSet(&[_]Feature{
|
|
.cx8,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const _i686 = CpuModel{
|
|
.name = "_i686",
|
|
.llvm_name = "i686",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const icelake_client = CpuModel{
|
|
.name = "icelake_client",
|
|
.llvm_name = "icelake-client",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx,
|
|
.avx2,
|
|
.avx512bitalg,
|
|
.avx512bw,
|
|
.avx512cd,
|
|
.avx512dq,
|
|
.avx512f,
|
|
.avx512ifma,
|
|
.avx512vbmi,
|
|
.avx512vbmi2,
|
|
.avx512vl,
|
|
.avx512vnni,
|
|
.avx512vpopcntdq,
|
|
.bmi,
|
|
.bmi2,
|
|
.clflushopt,
|
|
.clwb,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.fast_gather,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fast_vector_fsqrt,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.gfni,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.pku,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdpid,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sgx,
|
|
.sha,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.vaes,
|
|
.vpclmulqdq,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const icelake_server = CpuModel{
|
|
.name = "icelake_server",
|
|
.llvm_name = "icelake-server",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx,
|
|
.avx2,
|
|
.avx512bitalg,
|
|
.avx512bw,
|
|
.avx512cd,
|
|
.avx512dq,
|
|
.avx512f,
|
|
.avx512ifma,
|
|
.avx512vbmi,
|
|
.avx512vbmi2,
|
|
.avx512vl,
|
|
.avx512vnni,
|
|
.avx512vpopcntdq,
|
|
.bmi,
|
|
.bmi2,
|
|
.clflushopt,
|
|
.clwb,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.fast_gather,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fast_vector_fsqrt,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.gfni,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.pconfig,
|
|
.pku,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdpid,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sgx,
|
|
.sha,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.vaes,
|
|
.vpclmulqdq,
|
|
.wbnoinvd,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const ivybridge = CpuModel{
|
|
.name = "ivybridge",
|
|
.llvm_name = "ivybridge",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.avx,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.f16c,
|
|
.false_deps_popcnt,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.rdrnd,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.slow_unaligned_mem_32,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const k6 = CpuModel{
|
|
.name = "k6",
|
|
.llvm_name = "k6",
|
|
.features = featureSet(&[_]Feature{
|
|
.cx8,
|
|
.mmx,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const k6_2 = CpuModel{
|
|
.name = "k6_2",
|
|
.llvm_name = "k6-2",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnow",
|
|
.cx8,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const k6_3 = CpuModel{
|
|
.name = "k6_3",
|
|
.llvm_name = "k6-3",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnow",
|
|
.cx8,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const k8 = CpuModel{
|
|
.name = "k8",
|
|
.llvm_name = "k8",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const k8_sse3 = CpuModel{
|
|
.name = "k8_sse3",
|
|
.llvm_name = "k8-sse3",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const knl = CpuModel{
|
|
.name = "knl",
|
|
.llvm_name = "knl",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx512cd,
|
|
.avx512er,
|
|
.avx512f,
|
|
.avx512pf,
|
|
.bmi,
|
|
.bmi2,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.f16c,
|
|
.fast_gather,
|
|
.fast_partial_ymm_or_zmm_write,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.lzcnt,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prefetchwt1,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.slow_incdec,
|
|
.slow_pmaddwd,
|
|
.slow_two_mem_ops,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const knm = CpuModel{
|
|
.name = "knm",
|
|
.llvm_name = "knm",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx512cd,
|
|
.avx512er,
|
|
.avx512f,
|
|
.avx512pf,
|
|
.avx512vpopcntdq,
|
|
.bmi,
|
|
.bmi2,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.f16c,
|
|
.fast_gather,
|
|
.fast_partial_ymm_or_zmm_write,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.lzcnt,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prefetchwt1,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.slow_incdec,
|
|
.slow_pmaddwd,
|
|
.slow_two_mem_ops,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const lakemont = CpuModel{
|
|
.name = "lakemont",
|
|
.llvm_name = "lakemont",
|
|
.features = featureSet(&[_]Feature{}),
|
|
};
|
|
pub const nehalem = CpuModel{
|
|
.name = "nehalem",
|
|
.llvm_name = "nehalem",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fxsr,
|
|
.macrofusion,
|
|
.mmx,
|
|
.nopl,
|
|
.popcnt,
|
|
.sahf,
|
|
.sse4_2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const nocona = CpuModel{
|
|
.name = "nocona",
|
|
.llvm_name = "nocona",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.sse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const opteron = CpuModel{
|
|
.name = "opteron",
|
|
.llvm_name = "opteron",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const opteron_sse3 = CpuModel{
|
|
.name = "opteron_sse3",
|
|
.llvm_name = "opteron-sse3",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnowa",
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fast_scalar_shift_masks,
|
|
.fxsr,
|
|
.nopl,
|
|
.slow_shld,
|
|
.slow_unaligned_mem_16,
|
|
.sse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const penryn = CpuModel{
|
|
.name = "penryn",
|
|
.llvm_name = "penryn",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fxsr,
|
|
.macrofusion,
|
|
.mmx,
|
|
.nopl,
|
|
.sahf,
|
|
.slow_unaligned_mem_16,
|
|
.sse4_1,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentium = CpuModel{
|
|
.name = "pentium",
|
|
.llvm_name = "pentium",
|
|
.features = featureSet(&[_]Feature{
|
|
.cx8,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentium_m = CpuModel{
|
|
.name = "pentium_m",
|
|
.llvm_name = "pentium-m",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.sse2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentium_mmx = CpuModel{
|
|
.name = "pentium_mmx",
|
|
.llvm_name = "pentium-mmx",
|
|
.features = featureSet(&[_]Feature{
|
|
.cx8,
|
|
.mmx,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentium2 = CpuModel{
|
|
.name = "pentium2",
|
|
.llvm_name = "pentium2",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentium3 = CpuModel{
|
|
.name = "pentium3",
|
|
.llvm_name = "pentium3",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.sse,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentium3m = CpuModel{
|
|
.name = "pentium3m",
|
|
.llvm_name = "pentium3m",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.sse,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentium4 = CpuModel{
|
|
.name = "pentium4",
|
|
.llvm_name = "pentium4",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.sse2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentium4m = CpuModel{
|
|
.name = "pentium4m",
|
|
.llvm_name = "pentium4m",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.sse2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const pentiumpro = CpuModel{
|
|
.name = "pentiumpro",
|
|
.llvm_name = "pentiumpro",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const prescott = CpuModel{
|
|
.name = "prescott",
|
|
.llvm_name = "prescott",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.sse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const sandybridge = CpuModel{
|
|
.name = "sandybridge",
|
|
.llvm_name = "sandybridge",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.avx,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.false_deps_popcnt,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.slow_unaligned_mem_32,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsaveopt,
|
|
}),
|
|
};
|
|
pub const silvermont = CpuModel{
|
|
.name = "silvermont",
|
|
.llvm_name = "silvermont",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.false_deps_popcnt,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.sahf,
|
|
.slow_incdec,
|
|
.slow_lea,
|
|
.slow_pmulld,
|
|
.slow_two_mem_ops,
|
|
.sse4_2,
|
|
.ssse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const skx = CpuModel{
|
|
.name = "skx",
|
|
.llvm_name = "skx",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx,
|
|
.avx2,
|
|
.avx512bw,
|
|
.avx512cd,
|
|
.avx512dq,
|
|
.avx512f,
|
|
.avx512vl,
|
|
.bmi,
|
|
.bmi2,
|
|
.clflushopt,
|
|
.clwb,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.false_deps_popcnt,
|
|
.fast_gather,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fast_vector_fsqrt,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.pku,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const skylake = CpuModel{
|
|
.name = "skylake",
|
|
.llvm_name = "skylake",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx,
|
|
.avx2,
|
|
.bmi,
|
|
.bmi2,
|
|
.clflushopt,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.false_deps_popcnt,
|
|
.fast_gather,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fast_vector_fsqrt,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sgx,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const skylake_avx512 = CpuModel{
|
|
.name = "skylake_avx512",
|
|
.llvm_name = "skylake-avx512",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx,
|
|
.avx2,
|
|
.avx512bw,
|
|
.avx512cd,
|
|
.avx512dq,
|
|
.avx512f,
|
|
.avx512vl,
|
|
.bmi,
|
|
.bmi2,
|
|
.clflushopt,
|
|
.clwb,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.ermsb,
|
|
.f16c,
|
|
.false_deps_popcnt,
|
|
.fast_gather,
|
|
.fast_scalar_fsqrt,
|
|
.fast_shld_rotate,
|
|
.fast_variable_shuffle,
|
|
.fast_vector_fsqrt,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.invpcid,
|
|
.lzcnt,
|
|
.macrofusion,
|
|
.merge_to_threeway_branch,
|
|
.mmx,
|
|
.movbe,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.pku,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.slow_3ops_lea,
|
|
.sse4_2,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const slm = CpuModel{
|
|
.name = "slm",
|
|
.llvm_name = "slm",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.false_deps_popcnt,
|
|
.fxsr,
|
|
.idivq_to_divl,
|
|
.mmx,
|
|
.movbe,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.sahf,
|
|
.slow_incdec,
|
|
.slow_lea,
|
|
.slow_pmulld,
|
|
.slow_two_mem_ops,
|
|
.sse4_2,
|
|
.ssse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const tremont = CpuModel{
|
|
.name = "tremont",
|
|
.llvm_name = "tremont",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.aes,
|
|
.cldemote,
|
|
.clflushopt,
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.gfni,
|
|
.mmx,
|
|
.movbe,
|
|
.movdir64b,
|
|
.movdiri,
|
|
.mpx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.ptwrite,
|
|
.rdpid,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sgx,
|
|
.sha,
|
|
.slow_incdec,
|
|
.slow_lea,
|
|
.slow_two_mem_ops,
|
|
.sse4_2,
|
|
.ssse3,
|
|
.waitpkg,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const westmere = CpuModel{
|
|
.name = "westmere",
|
|
.llvm_name = "westmere",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx16,
|
|
.cx8,
|
|
.fxsr,
|
|
.macrofusion,
|
|
.mmx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.sahf,
|
|
.sse4_2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const winchip_c6 = CpuModel{
|
|
.name = "winchip_c6",
|
|
.llvm_name = "winchip-c6",
|
|
.features = featureSet(&[_]Feature{
|
|
.mmx,
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const winchip2 = CpuModel{
|
|
.name = "winchip2",
|
|
.llvm_name = "winchip2",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"3dnow",
|
|
.slow_unaligned_mem_16,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const x86_64 = CpuModel{
|
|
.name = "x86_64",
|
|
.llvm_name = "x86-64",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.macrofusion,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_3ops_lea,
|
|
.slow_incdec,
|
|
.sse2,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const yonah = CpuModel{
|
|
.name = "yonah",
|
|
.llvm_name = "yonah",
|
|
.features = featureSet(&[_]Feature{
|
|
.cmov,
|
|
.cx8,
|
|
.fxsr,
|
|
.mmx,
|
|
.nopl,
|
|
.slow_unaligned_mem_16,
|
|
.sse3,
|
|
.x87,
|
|
}),
|
|
};
|
|
pub const znver1 = CpuModel{
|
|
.name = "znver1",
|
|
.llvm_name = "znver1",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx2,
|
|
.bmi,
|
|
.bmi2,
|
|
.branchfusion,
|
|
.clflushopt,
|
|
.clzero,
|
|
.cmov,
|
|
.cx16,
|
|
.f16c,
|
|
.fast_15bytenop,
|
|
.fast_bextr,
|
|
.fast_lzcnt,
|
|
.fast_scalar_shift_masks,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.lzcnt,
|
|
.mmx,
|
|
.movbe,
|
|
.mwaitx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sha,
|
|
.slow_shld,
|
|
.sse4a,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
pub const znver2 = CpuModel{
|
|
.name = "znver2",
|
|
.llvm_name = "znver2",
|
|
.features = featureSet(&[_]Feature{
|
|
.@"64bit",
|
|
.adx,
|
|
.aes,
|
|
.avx2,
|
|
.bmi,
|
|
.bmi2,
|
|
.branchfusion,
|
|
.clflushopt,
|
|
.clwb,
|
|
.clzero,
|
|
.cmov,
|
|
.cx16,
|
|
.f16c,
|
|
.fast_15bytenop,
|
|
.fast_bextr,
|
|
.fast_lzcnt,
|
|
.fast_scalar_shift_masks,
|
|
.fma,
|
|
.fsgsbase,
|
|
.fxsr,
|
|
.lzcnt,
|
|
.mmx,
|
|
.movbe,
|
|
.mwaitx,
|
|
.nopl,
|
|
.pclmul,
|
|
.popcnt,
|
|
.prfchw,
|
|
.rdpid,
|
|
.rdrnd,
|
|
.rdseed,
|
|
.sahf,
|
|
.sha,
|
|
.slow_shld,
|
|
.sse4a,
|
|
.wbnoinvd,
|
|
.x87,
|
|
.xsave,
|
|
.xsavec,
|
|
.xsaveopt,
|
|
.xsaves,
|
|
}),
|
|
};
|
|
};
|
|
|
|
/// All x86 CPUs, sorted alphabetically by name.
|
|
/// TODO: Replace this with usage of `std.meta.declList`. It does work, but stage1
|
|
/// compiler has inefficient memory and CPU usage, affecting build times.
|
|
pub const all_cpus = &[_]*const CpuModel{
|
|
&cpu.amdfam10,
|
|
&cpu.athlon,
|
|
&cpu.athlon_4,
|
|
&cpu.athlon_fx,
|
|
&cpu.athlon_mp,
|
|
&cpu.athlon_tbird,
|
|
&cpu.athlon_xp,
|
|
&cpu.athlon64,
|
|
&cpu.athlon64_sse3,
|
|
&cpu.atom,
|
|
&cpu.barcelona,
|
|
&cpu.bdver1,
|
|
&cpu.bdver2,
|
|
&cpu.bdver3,
|
|
&cpu.bdver4,
|
|
&cpu.bonnell,
|
|
&cpu.broadwell,
|
|
&cpu.btver1,
|
|
&cpu.btver2,
|
|
&cpu.c3,
|
|
&cpu.c3_2,
|
|
&cpu.cannonlake,
|
|
&cpu.cascadelake,
|
|
&cpu.cooperlake,
|
|
&cpu.core_avx_i,
|
|
&cpu.core_avx2,
|
|
&cpu.core2,
|
|
&cpu.corei7,
|
|
&cpu.corei7_avx,
|
|
&cpu.generic,
|
|
&cpu.geode,
|
|
&cpu.goldmont,
|
|
&cpu.goldmont_plus,
|
|
&cpu.haswell,
|
|
&cpu._i386,
|
|
&cpu._i486,
|
|
&cpu._i586,
|
|
&cpu._i686,
|
|
&cpu.icelake_client,
|
|
&cpu.icelake_server,
|
|
&cpu.ivybridge,
|
|
&cpu.k6,
|
|
&cpu.k6_2,
|
|
&cpu.k6_3,
|
|
&cpu.k8,
|
|
&cpu.k8_sse3,
|
|
&cpu.knl,
|
|
&cpu.knm,
|
|
&cpu.lakemont,
|
|
&cpu.nehalem,
|
|
&cpu.nocona,
|
|
&cpu.opteron,
|
|
&cpu.opteron_sse3,
|
|
&cpu.penryn,
|
|
&cpu.pentium,
|
|
&cpu.pentium_m,
|
|
&cpu.pentium_mmx,
|
|
&cpu.pentium2,
|
|
&cpu.pentium3,
|
|
&cpu.pentium3m,
|
|
&cpu.pentium4,
|
|
&cpu.pentium4m,
|
|
&cpu.pentiumpro,
|
|
&cpu.prescott,
|
|
&cpu.sandybridge,
|
|
&cpu.silvermont,
|
|
&cpu.skx,
|
|
&cpu.skylake,
|
|
&cpu.skylake_avx512,
|
|
&cpu.slm,
|
|
&cpu.tremont,
|
|
&cpu.westmere,
|
|
&cpu.winchip_c6,
|
|
&cpu.winchip2,
|
|
&cpu.x86_64,
|
|
&cpu.yonah,
|
|
&cpu.znver1,
|
|
&cpu.znver2,
|
|
};
|