201 lines
5.8 KiB
ArmAsm
201 lines
5.8 KiB
ArmAsm
# REQUIRES: mips
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# Check generation of MIPS specific ELF header flags.
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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
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# RUN: %S/Inputs/mips-dynamic.s -o %t-so.o
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# RUN: ld.lld %t-so.o --gc-sections -shared -o %t.so
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# RUN: llvm-readobj -h -mips-abi-flags %t.so | FileCheck -check-prefix=SO %s
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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
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# RUN: ld.lld %t.o -o %t.exe
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# RUN: llvm-readobj -h -mips-abi-flags %t.exe | FileCheck -check-prefix=EXE %s
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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
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# RUN: -mcpu=mips32r2 %s -o %t-r2.o
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# RUN: ld.lld %t-r2.o -o %t-r2.exe
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# RUN: llvm-readobj -h -mips-abi-flags %t-r2.exe \
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# RUN: | FileCheck -check-prefix=EXE-R2 %s
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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
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# RUN: -mcpu=mips32r2 %s -o %t-r2.o
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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
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# RUN: -mcpu=mips32r5 %S/Inputs/mips-dynamic.s -o %t-r5.o
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# RUN: ld.lld %t-r2.o %t-r5.o -o %t-r5.exe
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# RUN: llvm-readobj -h -mips-abi-flags %t-r5.exe \
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# RUN: | FileCheck -check-prefix=EXE-R5 %s
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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
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# RUN: -mcpu=mips32r6 %s -o %t-r6.o
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# RUN: ld.lld %t-r6.o -o %t-r6.exe
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# RUN: llvm-readobj -h -mips-abi-flags %t-r6.exe \
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# RUN: | FileCheck -check-prefix=EXE-R6 %s
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# RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \
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# RUN: -position-independent -mcpu=octeon %s -o %t.o
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# RUN: ld.lld %t.o -o %t.exe
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# RUN: llvm-readobj -h -mips-abi-flags %t.exe \
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# RUN: | FileCheck -check-prefix=OCTEON %s
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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
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# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
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# RUN: -mattr=micromips %S/Inputs/mips-fpic.s -o %t-mm.o
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# RUN: ld.lld %t.o %t-mm.o -o %t.exe
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# RUN: llvm-readobj -h -mips-abi-flags %t.exe | FileCheck -check-prefix=MICRO %s
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.text
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.globl __start
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__start:
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nop
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# SO: Flags [
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# SO-NEXT: EF_MIPS_ABI_O32
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# SO-NEXT: EF_MIPS_ARCH_32
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# SO-NEXT: EF_MIPS_CPIC
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# SO-NEXT: EF_MIPS_PIC
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# SO-NEXT: ]
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# SO: MIPS ABI Flags {
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# SO-NEXT: Version: 0
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# SO-NEXT: ISA: MIPS32
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# SO-NEXT: ISA Extension: None
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# SO-NEXT: ASEs [
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# SO-NEXT: ]
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# SO-NEXT: FP ABI: Hard float (double precision)
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# SO-NEXT: GPR size: 32
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# SO-NEXT: CPR1 size: 32
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# SO-NEXT: CPR2 size: 0
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# SO-NEXT: Flags 1 [
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# SO-NEXT: ODDSPREG
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# SO-NEXT: ]
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# SO-NEXT: Flags 2: 0x0
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# SO-NEXT: }
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# EXE: Flags [
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# EXE-NEXT: EF_MIPS_ABI_O32
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# EXE-NEXT: EF_MIPS_ARCH_32
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# EXE-NEXT: EF_MIPS_CPIC
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# EXE-NEXT: ]
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# EXE: MIPS ABI Flags {
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# EXE-NEXT: Version: 0
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# EXE-NEXT: ISA: MIPS32
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# EXE-NEXT: ISA Extension: None
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# EXE-NEXT: ASEs [
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# EXE-NEXT: ]
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# EXE-NEXT: FP ABI: Hard float (double precision)
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# EXE-NEXT: GPR size: 32
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# EXE-NEXT: CPR1 size: 32
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# EXE-NEXT: CPR2 size: 0
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# EXE-NEXT: Flags 1 [
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# EXE-NEXT: ODDSPREG
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# EXE-NEXT: ]
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# EXE-NEXT: Flags 2: 0x0
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# EXE-NEXT: }
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# EXE-R2: Flags [
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# EXE-R2-NEXT: EF_MIPS_ABI_O32
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# EXE-R2-NEXT: EF_MIPS_ARCH_32R2
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# EXE-R2-NEXT: EF_MIPS_CPIC
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# EXE-R2-NEXT: ]
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# EXE-R2: MIPS ABI Flags {
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# EXE-R2-NEXT: Version: 0
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# EXE-R2-NEXT: ISA: MIPS32r2
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# EXE-R2-NEXT: ISA Extension: None
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# EXE-R2-NEXT: ASEs [
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# EXE-R2-NEXT: ]
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# EXE-R2-NEXT: FP ABI: Hard float (double precision)
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# EXE-R2-NEXT: GPR size: 32
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# EXE-R2-NEXT: CPR1 size: 32
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# EXE-R2-NEXT: CPR2 size: 0
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# EXE-R2-NEXT: Flags 1 [
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# EXE-R2-NEXT: ODDSPREG
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# EXE-R2-NEXT: ]
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# EXE-R2-NEXT: Flags 2: 0x0
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# EXE-R2-NEXT: }
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# EXE-R5: Flags [
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# EXE-R5-NEXT: EF_MIPS_ABI_O32
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# EXE-R5-NEXT: EF_MIPS_ARCH_32R2
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# EXE-R5-NEXT: EF_MIPS_CPIC
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# EXE-R5-NEXT: ]
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# EXE-R5: MIPS ABI Flags {
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# EXE-R5-NEXT: Version: 0
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# EXE-R5-NEXT: ISA: MIPS32r5
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# EXE-R5-NEXT: ISA Extension: None
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# EXE-R5-NEXT: ASEs [
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# EXE-R5-NEXT: ]
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# EXE-R5-NEXT: FP ABI: Hard float (double precision)
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# EXE-R5-NEXT: GPR size: 32
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# EXE-R5-NEXT: CPR1 size: 32
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# EXE-R5-NEXT: CPR2 size: 0
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# EXE-R5-NEXT: Flags 1 [
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# EXE-R5-NEXT: ODDSPREG
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# EXE-R5-NEXT: ]
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# EXE-R5-NEXT: Flags 2: 0x0
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# EXE-R5-NEXT: }
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# EXE-R6: Flags [
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# EXE-R6-NEXT: EF_MIPS_ABI_O32
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# EXE-R6-NEXT: EF_MIPS_ARCH_32R6
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# EXE-R6-NEXT: EF_MIPS_CPIC
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# EXE-R6-NEXT: EF_MIPS_NAN2008
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# EXE-R6-NEXT: ]
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# EXE-R6: MIPS ABI Flags {
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# EXE-R6-NEXT: Version: 0
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# EXE-R6-NEXT: ISA: MIPS32
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# EXE-R6-NEXT: ISA Extension: None
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# EXE-R6-NEXT: ASEs [
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# EXE-R6-NEXT: ]
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# EXE-R6-NEXT: FP ABI: Hard float (32-bit CPU, 64-bit FPU)
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# EXE-R6-NEXT: GPR size: 32
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# EXE-R6-NEXT: CPR1 size: 64
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# EXE-R6-NEXT: CPR2 size: 0
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# EXE-R6-NEXT: Flags 1 [
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# EXE-R6-NEXT: ODDSPREG
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# EXE-R6-NEXT: ]
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# EXE-R6-NEXT: Flags 2: 0x0
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# EXE-R6-NEXT: }
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# OCTEON: Flags [
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# OCTEON-NEXT: EF_MIPS_ARCH_64R2
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# OCTEON-NEXT: EF_MIPS_CPIC
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# OCTEON-NEXT: EF_MIPS_MACH_OCTEON
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# OCTEON-NEXT: EF_MIPS_PIC
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# OCTEON-NEXT: ]
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# OCTEON: MIPS ABI Flags {
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# OCTEON-NEXT: Version: 0
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# OCTEON-NEXT: ISA: MIPS64r2
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# OCTEON-NEXT: ISA Extension: Cavium Networks Octeon
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# OCTEON-NEXT: ASEs [
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# OCTEON-NEXT: ]
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# OCTEON-NEXT: FP ABI: Hard float (double precision)
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# OCTEON-NEXT: GPR size: 64
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# OCTEON-NEXT: CPR1 size: 64
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# OCTEON-NEXT: CPR2 size: 0
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# OCTEON-NEXT: Flags 1 [
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# OCTEON-NEXT: ODDSPREG
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# OCTEON-NEXT: ]
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# OCTEON-NEXT: Flags 2: 0x0
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# OCTEON-NEXT: }
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# MICRO: Flags [
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# MICRO-NEXT: EF_MIPS_ABI_O32
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# MICRO-NEXT: EF_MIPS_ARCH_32
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# MICRO-NEXT: EF_MIPS_CPIC
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# MICRO-NEXT: EF_MIPS_MICROMIPS
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# MICRO-NEXT: ]
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# MICRO: MIPS ABI Flags {
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# MICRO-NEXT: Version: 0
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# MICRO-NEXT: ISA: MIPS32
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# MICRO-NEXT: ISA Extension: None
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# MICRO-NEXT: ASEs [
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# MICRO-NEXT: microMIPS
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# MICRO-NEXT: ]
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# MICRO-NEXT: FP ABI: Hard float (double precision)
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# MICRO-NEXT: GPR size: 32
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# MICRO-NEXT: CPR1 size: 32
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# MICRO-NEXT: CPR2 size: 0
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# MICRO-NEXT: Flags 1 [
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# MICRO-NEXT: ODDSPREG
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# MICRO-NEXT: ]
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# MICRO-NEXT: Flags 2: 0x0
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# MICRO-NEXT: }
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