84f1893c18
in favor of CPU features. Also rearrange the `std.Target`
data structure.
* note: `@import("builtin")` was already deprecated in favor of
`@import("std").builtin`.
* `std.builtin.arch` is now deprecated in favor of
`std.builtin.cpu.arch`.
* `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`.
* `std.Target.CpuFeatures` is now `std.Target.Cpu`.
* `std.Target` no longer has an `arch` field. Instead it has a
`cpu` field, which has `arch`, `model`, and `features`.
* `std.Target` no longer has a `cpu_features` field.
* `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and
it is an enum instead of a tagged union.
* `std.Target.parseOs` is moved to `std.Target.Os.parse`.
* `std.Target.parseAbi` is moved to `std.Target.Abi.parse`.
* `std.Target.parseArchSub` is only for arch now and moved
to `std.Target.Cpu.Arch.parse`.
* `std.Target.parse` is improved to accept CPU name and features.
* `std.Target.Arch.getBaselineCpuFeatures` is moved to
`std.Target.Cpu.baseline`.
* `std.Target.allCpus` is renamed to `std.Target.allCpuModels`.
* `std.Target.defaultAbi` is moved to `std.Target.Abi.default`.
* Significant cleanup of aarch64 and arm CPU features, resulting in
the needed bit count for cpu feature set going from 174 to 138.
* Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging
feature sets together.
`-target-feature` and `-target-cpu` are removed in favor of
`-mcpu`, to conform to established conventions, and it gains
additional power to support cpu features. The syntax is:
-mcpu=name+on1+on2-off1-off2
closes #4261
314 lines
8.6 KiB
Zig
314 lines
8.6 KiB
Zig
const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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pub const Feature = enum {
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duplex,
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hvx,
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hvx_length128b,
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hvx_length64b,
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hvxv60,
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hvxv62,
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hvxv65,
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hvxv66,
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long_calls,
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mem_noshuf,
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memops,
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noreturn_stack_elim,
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nvj,
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nvs,
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packets,
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reserved_r19,
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small_data,
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v5,
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v55,
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v60,
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v62,
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v65,
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v66,
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zreg,
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};
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pub usingnamespace CpuFeature.feature_set_fns(Feature);
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pub const all_features = blk: {
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const len = @typeInfo(Feature).Enum.fields.len;
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std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
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var result: [len]CpuFeature = undefined;
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result[@enumToInt(Feature.duplex)] = .{
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.llvm_name = "duplex",
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.description = "Enable generation of duplex instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.hvx)] = .{
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.llvm_name = "hvx",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.hvx_length128b)] = .{
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.llvm_name = "hvx-length128b",
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.description = "Hexagon HVX 128B instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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}),
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};
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result[@enumToInt(Feature.hvx_length64b)] = .{
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.llvm_name = "hvx-length64b",
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.description = "Hexagon HVX 64B instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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}),
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};
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result[@enumToInt(Feature.hvxv60)] = .{
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.llvm_name = "hvxv60",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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}),
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};
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result[@enumToInt(Feature.hvxv62)] = .{
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.llvm_name = "hvxv62",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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.hvxv60,
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}),
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};
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result[@enumToInt(Feature.hvxv65)] = .{
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.llvm_name = "hvxv65",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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.hvxv60,
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.hvxv62,
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}),
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};
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result[@enumToInt(Feature.hvxv66)] = .{
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.llvm_name = "hvxv66",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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.hvxv60,
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.hvxv62,
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.hvxv65,
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.zreg,
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}),
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};
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result[@enumToInt(Feature.long_calls)] = .{
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.llvm_name = "long-calls",
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.description = "Use constant-extended calls",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.mem_noshuf)] = .{
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.llvm_name = "mem_noshuf",
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.description = "Supports mem_noshuf feature",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.memops)] = .{
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.llvm_name = "memops",
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.description = "Use memop instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.noreturn_stack_elim)] = .{
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.llvm_name = "noreturn-stack-elim",
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.description = "Eliminate stack allocation in a noreturn function when possible",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.nvj)] = .{
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.llvm_name = "nvj",
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.description = "Support for new-value jumps",
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.dependencies = featureSet(&[_]Feature{
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.packets,
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}),
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};
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result[@enumToInt(Feature.nvs)] = .{
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.llvm_name = "nvs",
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.description = "Support for new-value stores",
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.dependencies = featureSet(&[_]Feature{
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.packets,
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}),
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};
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result[@enumToInt(Feature.packets)] = .{
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.llvm_name = "packets",
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.description = "Support for instruction packets",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.reserved_r19)] = .{
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.llvm_name = "reserved-r19",
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.description = "Reserve register R19",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.small_data)] = .{
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.llvm_name = "small-data",
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.description = "Allow GP-relative addressing of global variables",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.v5)] = .{
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.llvm_name = "v5",
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.description = "Enable Hexagon V5 architecture",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.v55)] = .{
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.llvm_name = "v55",
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.description = "Enable Hexagon V55 architecture",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.v60)] = .{
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.llvm_name = "v60",
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.description = "Enable Hexagon V60 architecture",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.v62)] = .{
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.llvm_name = "v62",
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.description = "Enable Hexagon V62 architecture",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.v65)] = .{
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.llvm_name = "v65",
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.description = "Enable Hexagon V65 architecture",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.v66)] = .{
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.llvm_name = "v66",
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.description = "Enable Hexagon V66 architecture",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.zreg)] = .{
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.llvm_name = "zreg",
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.description = "Hexagon ZReg extension instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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const ti = @typeInfo(Feature);
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for (result) |*elem, i| {
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elem.index = i;
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elem.name = ti.Enum.fields[i].name;
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}
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break :blk result;
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};
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pub const cpu = struct {
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pub const generic = CpuModel{
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.name = "generic",
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.llvm_name = "generic",
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.features = featureSet(&[_]Feature{
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.duplex,
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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.v60,
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}),
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};
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pub const hexagonv5 = CpuModel{
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.name = "hexagonv5",
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.llvm_name = "hexagonv5",
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.features = featureSet(&[_]Feature{
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.duplex,
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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}),
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};
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pub const hexagonv55 = CpuModel{
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.name = "hexagonv55",
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.llvm_name = "hexagonv55",
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.features = featureSet(&[_]Feature{
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.duplex,
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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}),
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};
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pub const hexagonv60 = CpuModel{
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.name = "hexagonv60",
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.llvm_name = "hexagonv60",
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.features = featureSet(&[_]Feature{
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.duplex,
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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.v60,
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}),
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};
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pub const hexagonv62 = CpuModel{
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.name = "hexagonv62",
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.llvm_name = "hexagonv62",
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.features = featureSet(&[_]Feature{
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.duplex,
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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.v60,
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.v62,
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}),
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};
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pub const hexagonv65 = CpuModel{
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.name = "hexagonv65",
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.llvm_name = "hexagonv65",
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.features = featureSet(&[_]Feature{
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.duplex,
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.mem_noshuf,
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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.v60,
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.v62,
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.v65,
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}),
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};
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pub const hexagonv66 = CpuModel{
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.name = "hexagonv66",
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.llvm_name = "hexagonv66",
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.features = featureSet(&[_]Feature{
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.duplex,
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.mem_noshuf,
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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.v60,
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.v62,
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.v65,
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.v66,
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}),
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};
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};
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/// All hexagon CPUs, sorted alphabetically by name.
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/// TODO: Replace this with usage of `std.meta.declList`. It does work, but stage1
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/// compiler has inefficient memory and CPU usage, affecting build times.
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pub const all_cpus = &[_]*const CpuModel{
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&cpu.generic,
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&cpu.hexagonv5,
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&cpu.hexagonv55,
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&cpu.hexagonv60,
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&cpu.hexagonv62,
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&cpu.hexagonv65,
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&cpu.hexagonv66,
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};
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