221 lines
6.9 KiB
Zig
221 lines
6.9 KiB
Zig
const std = @import("std");
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const Type = @import("../Type.zig");
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const DW = std.dwarf;
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// zig fmt: off
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/// Definitions of all of the x64 registers. The order is semantically meaningful.
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/// The registers are defined such that IDs go in descending order of 64-bit,
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/// 32-bit, 16-bit, and then 8-bit, and each set contains exactly sixteen
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/// registers. This results in some useful properties:
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///
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/// Any 64-bit register can be turned into its 32-bit form by adding 16, and
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/// vice versa. This also works between 32-bit and 16-bit forms. With 8-bit, it
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/// works for all except for sp, bp, si, and di, which do *not* have an 8-bit
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/// form.
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///
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/// If (register & 8) is set, the register is extended.
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///
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/// The ID can be easily determined by figuring out what range the register is
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/// in, and then subtracting the base.
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pub const Register = enum(u8) {
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// 0 through 15, 64-bit registers. 8-15 are extended.
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// id is just the int value.
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rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi,
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r8, r9, r10, r11, r12, r13, r14, r15,
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// 16 through 31, 32-bit registers. 24-31 are extended.
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// id is int value - 16.
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eax, ecx, edx, ebx, esp, ebp, esi, edi,
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r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d,
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// 32-47, 16-bit registers. 40-47 are extended.
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// id is int value - 32.
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ax, cx, dx, bx, sp, bp, si, di,
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r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w,
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// 48-63, 8-bit registers. 56-63 are extended.
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// id is int value - 48.
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al, cl, dl, bl, ah, ch, dh, bh,
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r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b,
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/// Returns the bit-width of the register.
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pub fn size(self: Register) u7 {
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return switch (@enumToInt(self)) {
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0...15 => 64,
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16...31 => 32,
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32...47 => 16,
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48...64 => 8,
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else => unreachable,
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};
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}
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/// Returns whether the register is *extended*. Extended registers are the
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/// new registers added with amd64, r8 through r15. This also includes any
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/// other variant of access to those registers, such as r8b, r15d, and so
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/// on. This is needed because access to these registers requires special
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/// handling via the REX prefix, via the B or R bits, depending on context.
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pub fn isExtended(self: Register) bool {
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return @enumToInt(self) & 0x08 != 0;
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}
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/// This returns the 4-bit register ID, which is used in practically every
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/// opcode. Note that bit 3 (the highest bit) is *never* used directly in
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/// an instruction (@see isExtended), and requires special handling. The
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/// lower three bits are often embedded directly in instructions (such as
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/// the B8 variant of moves), or used in R/M bytes.
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pub fn id(self: Register) u4 {
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return @truncate(u4, @enumToInt(self));
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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return switch (self) {
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.rax, .eax, .ax, .al => 0,
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.rcx, .ecx, .cx, .cl => 1,
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.rdx, .edx, .dx, .dl => 2,
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.rsi, .esi, .si => 3,
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.rdi, .edi, .di => 4,
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.r8, .r8d, .r8w, .r8b => 5,
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.r9, .r9d, .r9w, .r9b => 6,
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.r10, .r10d, .r10w, .r10b => 7,
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.r11, .r11d, .r11w, .r11b => 8,
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else => null,
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};
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}
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/// Convert from any register to its 64 bit alias.
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pub fn to64(self: Register) Register {
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return @intToEnum(Register, self.id());
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}
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/// Convert from any register to its 32 bit alias.
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pub fn to32(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()) + 16);
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}
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/// Convert from any register to its 16 bit alias.
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pub fn to16(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()) + 32);
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}
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/// Convert from any register to its 8 bit alias.
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pub fn to8(self: Register) Register {
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return @intToEnum(Register, @as(u8, self.id()) + 48);
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}
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pub fn dwarfLocOp(self: Register) u8 {
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return switch (self.to64()) {
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.rax => DW.OP_reg0,
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.rdx => DW.OP_reg1,
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.rcx => DW.OP_reg2,
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.rbx => DW.OP_reg3,
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.rsi => DW.OP_reg4,
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.rdi => DW.OP_reg5,
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.rbp => DW.OP_reg6,
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.rsp => DW.OP_reg7,
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.r8 => DW.OP_reg8,
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.r9 => DW.OP_reg9,
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.r10 => DW.OP_reg10,
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.r11 => DW.OP_reg11,
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.r12 => DW.OP_reg12,
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.r13 => DW.OP_reg13,
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.r14 => DW.OP_reg14,
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.r15 => DW.OP_reg15,
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else => unreachable,
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};
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}
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};
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// zig fmt: on
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/// These registers belong to the called function.
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pub const callee_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8, .r9, .r10, .r11 };
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pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
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pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };
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// TODO add these registers to the enum and populate dwarfLocOp
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// // Return Address register. This is stored in `0(%rsp, "")` and is not a physical register.
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// RA = (16, "RA"),
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//
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// XMM0 = (17, "xmm0"),
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// XMM1 = (18, "xmm1"),
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// XMM2 = (19, "xmm2"),
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// XMM3 = (20, "xmm3"),
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// XMM4 = (21, "xmm4"),
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// XMM5 = (22, "xmm5"),
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// XMM6 = (23, "xmm6"),
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// XMM7 = (24, "xmm7"),
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//
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// XMM8 = (25, "xmm8"),
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// XMM9 = (26, "xmm9"),
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// XMM10 = (27, "xmm10"),
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// XMM11 = (28, "xmm11"),
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// XMM12 = (29, "xmm12"),
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// XMM13 = (30, "xmm13"),
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// XMM14 = (31, "xmm14"),
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// XMM15 = (32, "xmm15"),
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//
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// ST0 = (33, "st0"),
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// ST1 = (34, "st1"),
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// ST2 = (35, "st2"),
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// ST3 = (36, "st3"),
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// ST4 = (37, "st4"),
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// ST5 = (38, "st5"),
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// ST6 = (39, "st6"),
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// ST7 = (40, "st7"),
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//
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// MM0 = (41, "mm0"),
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// MM1 = (42, "mm1"),
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// MM2 = (43, "mm2"),
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// MM3 = (44, "mm3"),
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// MM4 = (45, "mm4"),
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// MM5 = (46, "mm5"),
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// MM6 = (47, "mm6"),
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// MM7 = (48, "mm7"),
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//
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// RFLAGS = (49, "rFLAGS"),
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// ES = (50, "es"),
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// CS = (51, "cs"),
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// SS = (52, "ss"),
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// DS = (53, "ds"),
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// FS = (54, "fs"),
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// GS = (55, "gs"),
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//
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// FS_BASE = (58, "fs.base"),
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// GS_BASE = (59, "gs.base"),
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//
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// TR = (62, "tr"),
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// LDTR = (63, "ldtr"),
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// MXCSR = (64, "mxcsr"),
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// FCW = (65, "fcw"),
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// FSW = (66, "fsw"),
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//
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// XMM16 = (67, "xmm16"),
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// XMM17 = (68, "xmm17"),
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// XMM18 = (69, "xmm18"),
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// XMM19 = (70, "xmm19"),
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// XMM20 = (71, "xmm20"),
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// XMM21 = (72, "xmm21"),
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// XMM22 = (73, "xmm22"),
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// XMM23 = (74, "xmm23"),
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// XMM24 = (75, "xmm24"),
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// XMM25 = (76, "xmm25"),
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// XMM26 = (77, "xmm26"),
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// XMM27 = (78, "xmm27"),
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// XMM28 = (79, "xmm28"),
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// XMM29 = (80, "xmm29"),
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// XMM30 = (81, "xmm30"),
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// XMM31 = (82, "xmm31"),
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//
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// K0 = (118, "k0"),
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// K1 = (119, "k1"),
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// K2 = (120, "k2"),
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// K3 = (121, "k3"),
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// K4 = (122, "k4"),
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// K5 = (123, "k5"),
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// K6 = (124, "k6"),
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// K7 = (125, "k7"),
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