* introduce a dump() function on Module.Fn which helpfully prints to
stderr the ZIR representation of a function (can be called before
attempting to codegen it). This is a debugging tool.
* implement x86 codegen for loops
* liveness: fix analysis of conditional branches. The logic was buggy
in a couple ways:
- it never actually saved the results into the IR instruction (fixed now)
- it incorrectly labeled operands as dying when their true death was
after the conditional branch ended (fixed now)
* zir rendering is enhanced to show liveness analysis results. this
helps when debugging liveness analysis.
* fix bug in zir rendering not numbering instructions correctly
closes#6021
* the .debug_line header is written properly
* link.File.Elf gains:
- SrcFn, which is now a field in Module.Fn
- SrcFile, which is now a field in Module.Scope.File
* link.File.Elf gets a whole *Package field rather than only
root_src_dir_path.
* the fields first_dbg_line_file and last_dbg_line_file tell where the
Line Number Program begins and ends, which alows moving files when
the header gets too big, and allows appending files to the end.
* codegen is passed a buffer for emitting .debug_line
Line Number Program opcodes for functions.
See #5963
There is some work-in-progress code here, but I need to go make some
experimental changes to changing how to represent source locations and I
want to do that in a separate commit.
* multiple returns jump to one canonical function exitlude. This is in
preparation for the defer feature.
* simple elision of trivial jump relocs.
* omit prelude/exitlude for naked calling convention functions.
* fix not switching on arch for prelude/exitlude
* fix swapped registers when setting stack mem from a register
* `optimize_mode` is passed to `link.File` and stored there
* improve the debugging function `Module.dumpInst`
* get rid of `Value.the_one_possible_value` in favor of a few more
specific values for different types. This is less buggy, one less
footgun.
* `Type.onePossibleValue` now returns a `?Value` instead of `bool`.
* codegen handles undefined values. `undef` is a new `MCValue` tag.
It uses 0xaa values depending on optimization mode. However
optimization mode does not yet support scope overrides.
* link.zig: move the `Options` field from `File.Elf` and `File.C` to
the base struct.
- fix the Tag enum to adhere to style conventions
* ZIR now supports emitting undefined values.
* Fix the logic of comptime math to properly compare against zero using
the `compareWithZero` function.
* implement sema for runtime deref, store pointer, coerce_to_ptr_elem,
and store
* identifiers support being lvalues, except for decls is still TODO
* codegen supports load, store, ref, alloc
* introduce more MCValue union tags to support pointers
* add load, ref, store typed IR instructions
* add Type.isVolatilePtr
Comment out non-x86_64 architectures for now in codegen.zig, because
they all have compile errors for their codepaths anyway, and it was
bloating the compilation speed and memory usage when stage1 tried to
build self-hosted. Here's the panic message:
"Backend architectures that don't have good support yet are commented
out, to improve compilation performance. If you are interested in one
of these other backends feel free to uncomment them. Eventually these
will be completed, but stage1 is slow and a memory hog."
This is a workaround to lower the time it takes to build self-hosted
with stage1 as well as use less memory. It should fix the CI.
Additionally:
* Add `single_mut_pointer` support to `Type`
* Trivial implementation of stack allocation in codegen.zig. It does
not deal with freeing yet, and it's missing the stack pointer
adjustment prologue.
* Add the `alloc` IR instruction and semantic analysis for `alloc` ZIR
instruction.
These are now supported enough that this example code hits the
limitations of the register allocator:
fn add(a: u32, b: u32) void {
const c = a + b; // 7
const d = a + c; // 10
const e = d + b; // 14
assert(e == 14);
}
// error: TODO implement copyToNewRegister
So now the next step is to implement register allocation as planned.
