74 Commits

Author SHA1 Message Date
Vexu
6ab0ac161e
stage2: slice return type analysis 2020-09-03 15:05:47 +03:00
Vexu
2a628fd401
stage2: astgen slice 2020-09-03 15:05:46 +03:00
Sahnvour
575fbd5e35 hash_map: rename to ArrayHashMap and add new HashMap implementation 2020-09-02 00:17:50 +02:00
Andrew Kelley
717b0e8275 stage2: introduce the ability for Scope.Block to be comptime
This gives zir_sema analysis the ability to check if the current scope
is expected to be comptime.
2020-08-31 23:34:58 -07:00
Vexu
fb28349349 stage2: astgen catch 2020-08-26 19:50:56 -07:00
Vexu
bcd04089eb stage2: add helpful error message for invalid for operands 2020-08-26 19:50:56 -07:00
Andrew Kelley
0c5faa61ae stage2: codegen: fix reuseOperand not doing death bookkeeping 2020-08-26 01:00:04 -07:00
Vexu
5de9aac749 stage2: error set types 2020-08-24 15:36:42 -07:00
Vexu
e9b15ac9a0 stage2: error set declarations 2020-08-24 15:36:42 -07:00
Vexu
16d7db59ed stage2: anyframe and error union types 2020-08-24 15:36:42 -07:00
Vexu
d62c12e077 stage2: astgen prefix ops 2020-08-24 15:36:42 -07:00
Vexu
d312d64c9a stage2: slice types 2020-08-20 16:42:48 -07:00
Vexu
9568248450 stage2: complex pointer types 2020-08-20 16:42:48 -07:00
Vexu
ebfe723f3c stage2: implement rest of simple pointer types 2020-08-20 16:42:48 -07:00
Andrew Kelley
9ec9c0f5e5 optimize the memory layout of Module.Fn and Module.Var
`is_pub` added to `Fn` would cost us an additional 8
bytes of memory per function, which is a real bummer
since it's only 1 bit of information.

If we wanted to really remove this, I suspect we could
make this a function isPub() which looks at the AST of
the corresponding Decl and finds if the FnProto AST node
has the pub token. However I saw an easier approach -

The data of whether something is pub or not is actually
a property of a Decl anyway, not a function, so we can
look at moving the field into Decl. Indeed, doing this,
we see that Decl already has deletion_flag: bool which
is hiding in the padding bytes between the enum (1 byte)
and the following u32 field (generation). So if we put
the is_pub bool there, it actually will take up no
additional space, with 1 byte of padding remaining.

This was an easy reworking of the code since any
func.is_pub could be changed simply to func.owner_decl.is_pub.

I also modified `Var` to make the init value non-optional
and moved the optional bit to a has_init: bool field. This is worse from
the perspective of control flow and safety, however it makes
`@sizeOf(Var)` go from 32 bytes to 24 bytes. The more code we can fit
into memory at once, the more justified we are in using the compiler as
a long-running process that does incremental updates.
2020-08-19 17:52:22 -07:00
Vexu
5fdcb1a792 stage2: emit zir variable fix, array type and enum literal support 2020-08-19 16:12:29 -07:00
Vexu
338a495648 stage2: implement global variables 2020-08-19 16:12:29 -07:00
Andrew Kelley
771f40204e
Merge pull request #6086 from Vexu/stage2
Stage2: more astgen stuff
2020-08-18 22:02:55 -04:00
Andrew Kelley
15bcfcd368 stage2: fix use-after-free when printing ZIR 2020-08-18 15:25:01 -07:00
Vexu
e4aefc6d0f
stage2: split ref from lvalue and add compile error for invalid assignments 2020-08-18 22:42:35 +03:00
Vexu
e0b01bd4a9
stage2: enum literals 2020-08-18 14:28:33 +03:00
Vexu
7c15c9428e
stage2: array types 2020-08-18 12:36:00 +03:00
Vexu
3eb8f7be10
stage2: astgen bool and/or 2020-08-18 11:38:56 +03:00
Vexu
0977e41407
stage2: ensure discarded error union payload is void 2020-08-18 10:36:57 +03:00
Vexu
ece4a2fc51
stage2: astgen for if and while with error unions 2020-08-17 14:28:04 +03:00
Vexu
012fac255f
stage2: fix optimization causing wrong optional child types 2020-08-17 14:26:32 +03:00
Vexu
c52513e25b
stage2: astgen for ptr types and address of 2020-08-17 14:24:56 +03:00
Andrew Kelley
28a9da8bfc stage2: implement while loops (bool condition)
* introduce a dump() function on Module.Fn which helpfully prints to
   stderr the ZIR representation of a function (can be called before
   attempting to codegen it). This is a debugging tool.
 * implement x86 codegen for loops
 * liveness: fix analysis of conditional branches. The logic was buggy
   in a couple ways:
   - it never actually saved the results into the IR instruction (fixed now)
   - it incorrectly labeled operands as dying when their true death was
     after the conditional branch ended (fixed now)
 * zir rendering is enhanced to show liveness analysis results. this
   helps when debugging liveness analysis.
 * fix bug in zir rendering not numbering instructions correctly

closes #6021
2020-08-13 20:32:32 -07:00
Andrew Kelley
fc402bdbbb stage2: zir_sema for loops
Also remove the "repeat" instruction and make it implied to be at the
end of a Loop body.
2020-08-13 20:32:32 -07:00
Andrew Kelley
ec4953504a stage2: implement safety checks at the zir_sema level 2020-08-13 10:04:46 -07:00
Vexu
6b2ce9d1e9 stage2: split unwrap_optional to safe and unsafe verions 2020-08-13 08:12:17 -07:00
Vexu
4a40282391 stage2: implement unwrap optional 2020-08-13 08:12:17 -07:00
Vexu
5c1fe58613 stage2: gen optional types 2020-08-13 08:12:17 -07:00
Andrew Kelley
de4f3f11f7 stage2: astgen for while loops
See #6021
2020-08-12 21:13:16 -07:00
Andrew Kelley
8282f4271c stage2: basic support for parameters .debug_info
see #6014
2020-08-11 22:23:32 -07:00
Andrew Kelley
659603c621 codegen: emit .debug_line ops for IR instructions 2020-08-02 21:28:06 -07:00
Andrew Kelley
4beff80b2f stage2: codegen handles undefined values
* `optimize_mode` is passed to `link.File` and stored there
 * improve the debugging function `Module.dumpInst`
 * get rid of `Value.the_one_possible_value` in favor of a few more
   specific values for different types. This is less buggy, one less
   footgun.
 * `Type.onePossibleValue` now returns a `?Value` instead of `bool`.
 * codegen handles undefined values. `undef` is a new `MCValue` tag.
   It uses 0xaa values depending on optimization mode. However
   optimization mode does not yet support scope overrides.
 * link.zig: move the `Options` field from `File.Elf` and `File.C` to
   the base struct.
   - fix the Tag enum to adhere to style conventions
 * ZIR now supports emitting undefined values.
 * Fix the logic of comptime math to properly compare against zero using
   the `compareWithZero` function.
2020-07-29 02:29:37 -07:00
Andrew Kelley
2b8e7deeda stage2: add ZIR emitType support for simple pointer types 2020-07-29 02:29:37 -07:00
Andrew Kelley
5ccee4c986 stage2: more progress towards mutable local variables
* implement sema for runtime deref, store pointer, coerce_to_ptr_elem,
   and store
 * identifiers support being lvalues, except for decls is still TODO
 * codegen supports load, store, ref, alloc
 * introduce more MCValue union tags to support pointers
 * add load, ref, store typed IR instructions
 * add Type.isVolatilePtr
2020-07-29 02:29:36 -07:00
Andrew Kelley
d726c2a2d3 self-hosted: beginnings of stack allocation
Comment out non-x86_64 architectures for now in codegen.zig, because
they all have compile errors for their codepaths anyway, and it was
bloating the compilation speed and memory usage when stage1 tried to
build self-hosted. Here's the panic message:

"Backend architectures that don't have good support yet are commented
out, to improve compilation performance. If you are interested in one
of these other backends feel free to uncomment them. Eventually these
will be completed, but stage1 is slow and a memory hog."

This is a workaround to lower the time it takes to build self-hosted
with stage1 as well as use less memory. It should fix the CI.

Additionally:
 * Add `single_mut_pointer` support to `Type`
 * Trivial implementation of stack allocation in codegen.zig. It does
   not deal with freeing yet, and it's missing the stack pointer
   adjustment prologue.
 * Add the `alloc` IR instruction and semantic analysis for `alloc` ZIR
   instruction.
2020-07-28 01:43:04 -07:00
Andrew Kelley
488df7f1d1 stage2: astgen for all arithmetic and assignments 2020-07-27 17:09:47 -07:00
Andrew Kelley
aac6e8c418 self-hosted: AST flattening, astgen improvements, result locations, and more
* AST: flatten ControlFlowExpression into Continue, Break, and Return.
 * AST: unify identifiers and literals into the same AST type: OneToken
 * AST: ControlFlowExpression uses TrailerFlags to optimize storage
   space.
 * astgen: support `var` as well as `const` locals, and support
   explicitly typed locals. Corresponding Module and codegen code is not
   implemented yet.
 * astgen: support result locations.
 * ZIR: add the following instructions (see the corresponding doc
   comments for explanations of semantics):
   - alloc
   - alloc_inferred
   - bitcast_result_ptr
   - coerce_result_block_ptr
   - coerce_result_ptr
   - coerce_to_ptr_elem
   - ensure_result_used
   - ensure_result_non_error
   - ret_ptr
   - ret_type
   - store
   - param_type
 * the skeleton structure for result locations is set up. It's looking
   pretty clean so far.
 * add compile error for unused result and compile error for discarding
   errors.
 * astgen: split builtin calls up to implemented manually, and implement
   `@as`, `@bitCast` (and others) with respect to result locations.
 * add CLI support for hex and raw object formats. They are not
   supported by the self-hosted compiler yet, and emit errors.
 * rename `--c` CLI to `-ofmt=[objectformat]` which can be any of the
   object formats. Only ELF and C are supported so far. Also added missing
   help to the help text.
 * Remove hard tabs from C backend test cases. Shame on you Noam, you
   are grounded, you should know better, etc. Bad boy.
 * Delete C backend code and test case that relied on comptime_int
   incorrectly making it all the way to codegen.
2020-07-23 23:05:26 -07:00
Vexu
7e7d1df4da
stage2: add floatCast to zir and ir 2020-07-21 22:34:12 +03:00
Vexu
7b52dbbf83
stage2: implement some casts for numbers 2020-07-21 22:29:29 +03:00
Andrew Kelley
8ee629aa4c stage2: ability for ZIR to map multiple tags to the same type 2020-07-21 12:13:15 -07:00
Andrew Kelley
ef91b11295 stage2: register allocator processes operand deaths
also rework the IR data structures
2020-07-20 13:12:20 -07:00
pfg
01ab167ce3 stage2: change large switch → inline for loop 2020-07-16 10:32:24 +00:00
Andrew Kelley
d29dd5834b stage2: local consts
These are now supported enough that this example code hits the
limitations of the register allocator:

fn add(a: u32, b: u32) void {
    const c = a + b; // 7
    const d = a + c; // 10
    const e = d + b; // 14
    assert(e == 14);
}
// error: TODO implement copyToNewRegister

So now the next step is to implement register allocation as planned.
2020-07-15 22:36:35 -07:00
Andrew Kelley
4f5e065d6e stage2: add ZIR support for BoolNot 2020-07-13 20:47:47 -07:00
Andrew Kelley
25b1c00c72 stage2: add implicit return void where applicable 2020-07-13 00:08:21 -07:00