Vexu
2a628fd401
stage2: astgen slice
2020-09-03 15:05:46 +03:00
Vexu
ff7c6e1e3c
stage2: astgen orelse
2020-09-03 15:05:43 +03:00
Andrew Kelley
717b0e8275
stage2: introduce the ability for Scope.Block to be comptime
...
This gives zir_sema analysis the ability to check if the current scope
is expected to be comptime.
2020-08-31 23:34:58 -07:00
Tadeo Kondrak
d3e5105ecc
std.zig.ast: make getTrailer/setTrailer private and add getters/setters
2020-08-30 17:18:25 -06:00
Tadeo Kondrak
3c87872dc5
stage2: Update to new std.meta.TrailerFlags API
2020-08-27 15:21:19 -06:00
Vexu
cc26cb9b23
stage2: codegen needed for basic for loop
2020-08-26 19:50:56 -07:00
Vexu
fb28349349
stage2: astgen catch
2020-08-26 19:50:56 -07:00
Vexu
bf014d529a
stage2: array access astgen
2020-08-26 19:50:56 -07:00
Vexu
bcd04089eb
stage2: add helpful error message for invalid for operands
2020-08-26 19:50:56 -07:00
Vexu
b1aa2857ff
stage2: astgen for loops
2020-08-26 19:50:56 -07:00
Andrew Kelley
b68fa9970b
stage2 codegen: Rework genCondBr
...
so that the arch-independent logic isn't buried and duplicated.
2020-08-25 22:44:18 -07:00
Andrew Kelley
84d50c892d
stage2: astgen: kill the "lvalue" ResultLoc tag
2020-08-24 16:13:10 -07:00
Vexu
1520e084cb
stage2: implement accessing error values
2020-08-24 15:36:42 -07:00
Vexu
e9b15ac9a0
stage2: error set declarations
2020-08-24 15:36:42 -07:00
Vexu
16d7db59ed
stage2: anyframe and error union types
2020-08-24 15:36:42 -07:00
Vexu
d62c12e077
stage2: astgen prefix ops
2020-08-24 15:36:42 -07:00
Vexu
d312d64c9a
stage2: slice types
2020-08-20 16:42:48 -07:00
Vexu
9568248450
stage2: complex pointer types
2020-08-20 16:42:48 -07:00
Vexu
ebfe723f3c
stage2: implement rest of simple pointer types
2020-08-20 16:42:48 -07:00
Vexu
ab8a9a6605
stage2: fix astgen of decl ref, add test for global consts
2020-08-19 16:12:29 -07:00
Vexu
e4aefc6d0f
stage2: split ref from lvalue and add compile error for invalid assignments
2020-08-18 22:42:35 +03:00
Vexu
2b45e23477
stage2: character literals and multiline strings
2020-08-18 20:10:18 +03:00
Vexu
e0b01bd4a9
stage2: enum literals
2020-08-18 14:28:33 +03:00
Vexu
7c15c9428e
stage2: array types
2020-08-18 12:36:00 +03:00
Vexu
3eb8f7be10
stage2: astgen bool and/or
2020-08-18 11:38:56 +03:00
Vexu
0977e41407
stage2: ensure discarded error union payload is void
2020-08-18 10:36:57 +03:00
Veikka Tuominen
d8fb377e2a
Merge pull request #6060 from Vexu/stage2
...
Stage2: more optionals stuff
2020-08-18 00:15:36 +03:00
Vexu
13b2f1e90b
address review feedback
2020-08-17 19:21:03 +03:00
Vexu
ece4a2fc51
stage2: astgen for if and while with error unions
2020-08-17 14:28:04 +03:00
Vexu
db77b6b4e7
stage2: astgen for if and while with optionals
2020-08-17 14:28:04 +03:00
Vexu
012fac255f
stage2: fix optimization causing wrong optional child types
2020-08-17 14:26:32 +03:00
Vexu
c52513e25b
stage2: astgen for ptr types and address of
2020-08-17 14:24:56 +03:00
Noam Preil
3ca8c42e7a
Astgen: further cleanup
2020-08-16 20:36:33 -04:00
Noam Preil
692f38c250
astgen: minor cleanup
2020-08-16 20:32:50 -04:00
Andrew Kelley
66d76cc4f9
stage2: codegen for labeled blocks
2020-08-15 17:03:05 -07:00
Andrew Kelley
0f3f96c850
stage2: astgen for labeled blocks and labeled breaks
2020-08-15 00:52:25 -07:00
Andrew Kelley
f356cba704
stage2: populate some of the astgen switch possibilities
...
Idea here is simply to entice people to contribute astgen code :)
2020-08-14 22:50:00 -04:00
Andrew Kelley
b49d3672f3
stage2 astgen for LabeledBlock
2020-08-14 22:50:00 -04:00
Andrew Kelley
9a5a1013a8
std.zig.ast: extract out Node.LabeledBlock from Node.Block
...
This is part of an ongoing effort to reduce size of in-memory AST. This
enum flattening pattern is widespread throughout the self-hosted
compiler.
This is a API breaking change for consumers of the self-hosted parser.
2020-08-14 22:50:00 -04:00
Andrew Kelley
5f7c7191ab
stage2: astgen for non-labeled blocks
2020-08-14 11:28:40 -07:00
Andrew Kelley
fc402bdbbb
stage2: zir_sema for loops
...
Also remove the "repeat" instruction and make it implied to be at the
end of a Loop body.
2020-08-13 20:32:32 -07:00
Vexu
6b2ce9d1e9
stage2: split unwrap_optional to safe and unsafe verions
2020-08-13 08:12:17 -07:00
Vexu
4a40282391
stage2: implement unwrap optional
2020-08-13 08:12:17 -07:00
Vexu
5c1fe58613
stage2: gen optional types
2020-08-13 08:12:17 -07:00
Andrew Kelley
de4f3f11f7
stage2: astgen for while loops
...
See #6021
2020-08-12 21:13:16 -07:00
Andrew Kelley
659603c621
codegen: emit .debug_line ops for IR instructions
2020-08-02 21:28:06 -07:00
Andrew Kelley
64a1a280ef
stage2: fix superfluous returnvoid ZIR
2020-07-29 02:29:37 -07:00
Andrew Kelley
5ccee4c986
stage2: more progress towards mutable local variables
...
* implement sema for runtime deref, store pointer, coerce_to_ptr_elem,
and store
* identifiers support being lvalues, except for decls is still TODO
* codegen supports load, store, ref, alloc
* introduce more MCValue union tags to support pointers
* add load, ref, store typed IR instructions
* add Type.isVolatilePtr
2020-07-29 02:29:36 -07:00
Andrew Kelley
0965724e31
self-hosted: refactor some code out of Module.zig into zir_sema.zig
...
This makes sense from an organizational point of view, as explained by
this new doc comment at the top of the new file:
//! Semantic analysis of ZIR instructions.
//! This file operates on a `Module` instance, transforming untyped ZIR
//! instructions into semantically-analyzed IR instructions. It does type
//! checking, comptime control flow, and safety-check generation. This is the
//! the heart of the Zig compiler.
//! When deciding if something goes into this file or into Module, here is a
//! guiding principle: if it has to do with (untyped) ZIR instructions, it goes
//! here. If the analysis operates on typed IR instructions, it goes in Module.
Before:
4009 src-self-hosted/Module.zig
After:
2776 src-self-hosted/Module.zig
1128 src-self-hosted/zir_sema.zig
This should be sufficient to avoid the situation we have in stage1 where
ir.cpp is 32,516 lines.
2020-07-27 22:44:18 -07:00
Andrew Kelley
488df7f1d1
stage2: astgen for all arithmetic and assignments
2020-07-27 17:09:47 -07:00
