Commit Graph

1009 Commits (937c02f185d66051e4ff01b7b1da9c7cf6c76b70)

Author SHA1 Message Date
Andrew Kelley aac6e8c418 self-hosted: AST flattening, astgen improvements, result locations, and more
* AST: flatten ControlFlowExpression into Continue, Break, and Return.
 * AST: unify identifiers and literals into the same AST type: OneToken
 * AST: ControlFlowExpression uses TrailerFlags to optimize storage
   space.
 * astgen: support `var` as well as `const` locals, and support
   explicitly typed locals. Corresponding Module and codegen code is not
   implemented yet.
 * astgen: support result locations.
 * ZIR: add the following instructions (see the corresponding doc
   comments for explanations of semantics):
   - alloc
   - alloc_inferred
   - bitcast_result_ptr
   - coerce_result_block_ptr
   - coerce_result_ptr
   - coerce_to_ptr_elem
   - ensure_result_used
   - ensure_result_non_error
   - ret_ptr
   - ret_type
   - store
   - param_type
 * the skeleton structure for result locations is set up. It's looking
   pretty clean so far.
 * add compile error for unused result and compile error for discarding
   errors.
 * astgen: split builtin calls up to implemented manually, and implement
   `@as`, `@bitCast` (and others) with respect to result locations.
 * add CLI support for hex and raw object formats. They are not
   supported by the self-hosted compiler yet, and emit errors.
 * rename `--c` CLI to `-ofmt=[objectformat]` which can be any of the
   object formats. Only ELF and C are supported so far. Also added missing
   help to the help text.
 * Remove hard tabs from C backend test cases. Shame on you Noam, you
   are grounded, you should know better, etc. Bad boy.
 * Delete C backend code and test case that relied on comptime_int
   incorrectly making it all the way to codegen.
2020-07-23 23:05:26 -07:00
Vexu dd89297388
stage2: actually implement float casting 2020-07-21 22:34:14 +03:00
Vexu c29c79b17a
stage2: remove some dead code, fix build on aarch64 2020-07-21 22:34:14 +03:00
Vexu 7e7d1df4da
stage2: add floatCast to zir and ir 2020-07-21 22:34:12 +03:00
Vexu 7b52dbbf83
stage2: implement some casts for numbers 2020-07-21 22:29:29 +03:00
Vexu da217fadeb
stage2: astgen for floats and other primitive literals 2020-07-21 22:29:28 +03:00
Vexu e77ca6af70
stage2: add float values 2020-07-21 22:29:28 +03:00
Andrew Kelley 8ee629aa4c stage2: ability for ZIR to map multiple tags to the same type 2020-07-21 12:13:15 -07:00
Andrew Kelley 7a1a924788 stage2: AST: (breaking) flatten out suffix operations 2020-07-21 10:52:24 -07:00
Andrew Kelley 1ac28eed83 stage2 AST: rename OptionalUnwrap to OrElse
preparing to flatten suffix operations AST
2020-07-21 10:46:47 -07:00
Andrew Kelley 1cfe43d563
Merge pull request #5888 from pfgithub/stage-2-testing-Copy
stage2: period and suffixop
2020-07-21 17:42:46 +00:00
Andrew Kelley ef91b11295 stage2: register allocator processes operand deaths
also rework the IR data structures
2020-07-20 13:12:20 -07:00
Andrew Kelley a8065a05a5 stage2: fix implementation of liveness operandDies() 2020-07-20 13:12:20 -07:00
Andrew Kelley 896472c20e stage2: implement register copying 2020-07-20 13:12:20 -07:00
Andrew Kelley ef9aeb6ac4 stage2: codegen: refactor to always have comptime arch 2020-07-20 13:12:20 -07:00
pfg 86922b8d08 stage2: support @"identifier" syntax 2020-07-16 14:08:36 -07:00
Vexu 37647375dc
translate-c: support initializer list expr macros 2020-07-16 16:20:47 +03:00
pfg 83a0073b68 stage2: period and suffixop 2020-07-16 04:22:05 -07:00
pfg 01ab167ce3 stage2: change large switch → inline for loop 2020-07-16 10:32:24 +00:00
Andrew Kelley d29dd5834b stage2: local consts
These are now supported enough that this example code hits the
limitations of the register allocator:

fn add(a: u32, b: u32) void {
    const c = a + b; // 7
    const d = a + c; // 10
    const e = d + b; // 14
    assert(e == 14);
}
// error: TODO implement copyToNewRegister

So now the next step is to implement register allocation as planned.
2020-07-15 22:36:35 -07:00
Andrew Kelley af12596e8d stage2: breaking AST memory layout modifications
InfixOp is flattened out so that each operator is an independent AST
node tag. The two kinds of structs are now Catch and SimpleInfixOp.

Beginning implementation of supporting codegen for const locals.
2020-07-15 19:39:18 -07:00
Andrew Kelley f119092273 stage2: breaking AST memory layout modifications
ast.Node.Id => ast.Node.Tag, matching recent style conventions.

Now multiple different AST node tags can map to the same AST node data
structures. In this commit, simple prefix operators now all map top
SimplePrefixOp.

`ast.Node.castTag` is now preferred over `ast.Node.cast`.

Upcoming: InfixOp flattened out.
2020-07-15 18:15:59 -07:00
Andrew Kelley e70d6d19f5 stage2: extract AST=>ZIR code to separate file 2020-07-15 15:42:02 -07:00
Andrew Kelley 804b51b179 stage2: VarDecl and FnProto take advantage of TrailerFlags API
These AST nodes now have a flags field and then a bunch of optional
trailing objects. The end result is lower memory usage and consequently
better performance. This is part of an ongoing effort to reduce the
amount of memory parsed ASTs take up.

Running `zig fmt` on the std lib:
 * cache-misses: 2,554,321 => 2,534,745
 * instructions: 3,293,220,119 => 3,302,479,874
 * peak memory: 74.0 MiB => 73.0 MiB

Holding the entire std lib AST in memory at the same time:

  93.9 MiB => 88.5 MiB
2020-07-15 02:07:30 -07:00
Andrew Kelley a92990f993 stage2: implement enough for assert() function to codegen 2020-07-14 02:24:12 -07:00
Andrew Kelley 135580c162 stage2: fix liveness analysis of Call instructions 2020-07-13 23:48:54 -07:00
Andrew Kelley 5da5ded743 stage2: detect unreferenced non-volatile asm and NOT 2020-07-13 23:48:26 -07:00
Andrew Kelley 4f5e065d6e stage2: add ZIR support for BoolNot 2020-07-13 20:47:47 -07:00
Andrew Kelley 14cef9dd3d stage2 parser: split out PrefixOp into separate AST Nodes
This is part of a larger effort to improve the memory layout of AST
nodes of the self-hosted parser to reduce wasted memory. Reduction of
wasted memory also translates to improved performance because of fewer
memory allocations, and fewer cache misses.

Compared to master, when running `zig fmt` on the std lib:

 * cache-misses: 801,829 => 768,624
 * instructions: 3,234,877,167 => 3,232,075,022
 * peak memory: 81480 KB => 75964 KB
2020-07-13 20:13:51 -07:00
Andrew Kelley 204f61d7f5 stage2: Module: use StringHashMapUnmanaged 2020-07-13 15:34:31 -07:00
Andrew Kelley 08154c0deb stage2: add retvoid support to CBE 2020-07-13 00:28:11 -07:00
Andrew Kelley 25b1c00c72 stage2: add implicit return void where applicable 2020-07-13 00:08:21 -07:00
Andrew Kelley c306392b44 stage2: codegen: more branching support 2020-07-13 00:08:21 -07:00
Andrew Kelley b75a51f94b stage2: implement function calling convention for calls 2020-07-13 00:08:21 -07:00
Andrew Kelley 8fe63d5042 stage2: peer type resolution with noreturn 2020-07-13 00:08:21 -07:00
Noam Preil 8d6cadee16
CBE: Code cleanup 2020-07-13 01:49:04 -04:00
Noam Preil 4a46248198
CBE: Only generate `(void)` for calls whose return values are ignored 2020-07-13 01:49:04 -04:00
Noam Preil a124b027b4
CBE: Use hasCodeGenBits instead of checking against void and noreturn 2020-07-13 01:49:04 -04:00
Noam Preil 3bad1c16cc
Get basic return test working 2020-07-13 01:49:04 -04:00
pixelherodev 2c882b2e65
CBE: Make C an ObjectFormat instead of a special bool (#5849) 2020-07-12 22:56:31 -04:00
Vexu be1507a7af
update compile error tests and some doc comments 2020-07-12 00:54:07 +03:00
Vexu 3e095d8ef3
use 'anytype' in translate-c 2020-07-11 22:04:38 +03:00
Vexu e85fe13e44
run zig fmt on std lib and self hosted 2020-07-11 20:41:19 +03:00
Andrew Kelley 7bd0500589 Merge remote-tracking branch 'origin/master' into register-allocation 2020-07-08 20:46:06 -07:00
Andrew Kelley 8e425c0c8d stage2: `if` AST=>ZIR 2020-07-08 20:33:33 -07:00
Noam Preil d060be8804
CBE: Don't expose openCFile, always close file after an update 2020-07-08 14:10:11 -04:00
Noam Preil 6b48634166
CBE: Emit asm decls for now, but rename to make them valid 2020-07-08 14:05:07 -04:00
Andrew Kelley be0546d877 stage2: implement compare operator AST->ZIR 2020-07-08 07:04:43 +00:00
Andrew Kelley 5e60872060 stage2 misc fixes 2020-07-08 06:56:20 +00:00
Andrew Kelley 8849604131 stage2: proper indenting when printing ZIR text 2020-07-08 05:44:51 +00:00