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73 Commits

Author SHA1 Message Date
Vexu
7e7d1df4da
stage2: add floatCast to zir and ir 2020-07-21 22:34:12 +03:00
Vexu
7b52dbbf83
stage2: implement some casts for numbers 2020-07-21 22:29:29 +03:00
Andrew Kelley
8ee629aa4c stage2: ability for ZIR to map multiple tags to the same type 2020-07-21 12:13:15 -07:00
Andrew Kelley
ef91b11295 stage2: register allocator processes operand deaths 
also rework the IR data structures
 2020-07-20 13:12:20 -07:00
Andrew Kelley
d29dd5834b stage2: local consts 
These are now supported enough that this example code hits the
limitations of the register allocator:

fn add(a: u32, b: u32) void {
    const c = a + b; // 7
    const d = a + c; // 10
    const e = d + b; // 14
    assert(e == 14);
}
// error: TODO implement copyToNewRegister

So now the next step is to implement register allocation as planned.
 2020-07-15 22:36:35 -07:00
Andrew Kelley
af12596e8d stage2: breaking AST memory layout modifications 
InfixOp is flattened out so that each operator is an independent AST
node tag. The two kinds of structs are now Catch and SimpleInfixOp.

Beginning implementation of supporting codegen for const locals.
 2020-07-15 19:39:18 -07:00
Andrew Kelley
f119092273 stage2: breaking AST memory layout modifications 
ast.Node.Id => ast.Node.Tag, matching recent style conventions.

Now multiple different AST node tags can map to the same AST node data
structures. In this commit, simple prefix operators now all map top
SimplePrefixOp.

`ast.Node.castTag` is now preferred over `ast.Node.cast`.

Upcoming: InfixOp flattened out.
 2020-07-15 18:15:59 -07:00
Andrew Kelley
e70d6d19f5 stage2: extract AST=>ZIR code to separate file 2020-07-15 15:42:02 -07:00
Andrew Kelley
804b51b179 stage2: VarDecl and FnProto take advantage of TrailerFlags API 
These AST nodes now have a flags field and then a bunch of optional
trailing objects. The end result is lower memory usage and consequently
better performance. This is part of an ongoing effort to reduce the
amount of memory parsed ASTs take up.

Running `zig fmt` on the std lib:
 * cache-misses: 2,554,321 => 2,534,745
 * instructions: 3,293,220,119 => 3,302,479,874
 * peak memory: 74.0 MiB => 73.0 MiB

Holding the entire std lib AST in memory at the same time:

  93.9 MiB => 88.5 MiB
 2020-07-15 02:07:30 -07:00
Andrew Kelley
a92990f993 stage2: implement enough for assert() function to codegen 2020-07-14 02:24:12 -07:00
Andrew Kelley
4f5e065d6e stage2: add ZIR support for BoolNot 2020-07-13 20:47:47 -07:00
Andrew Kelley
14cef9dd3d stage2 parser: split out PrefixOp into separate AST Nodes 
This is part of a larger effort to improve the memory layout of AST
nodes of the self-hosted parser to reduce wasted memory. Reduction of
wasted memory also translates to improved performance because of fewer
memory allocations, and fewer cache misses.

Compared to master, when running `zig fmt` on the std lib:

 * cache-misses: 801,829 => 768,624
 * instructions: 3,234,877,167 => 3,232,075,022
 * peak memory: 81480 KB => 75964 KB
 2020-07-13 20:13:51 -07:00
Andrew Kelley
204f61d7f5 stage2: Module: use StringHashMapUnmanaged 2020-07-13 15:34:31 -07:00
Andrew Kelley
08154c0deb stage2: add retvoid support to CBE 2020-07-13 00:28:11 -07:00
Andrew Kelley
25b1c00c72 stage2: add implicit return void where applicable 2020-07-13 00:08:21 -07:00
Andrew Kelley
8fe63d5042 stage2: peer type resolution with noreturn 2020-07-13 00:08:21 -07:00
Noam Preil
3bad1c16cc
Get basic return test working 2020-07-13 01:49:04 -04:00
pixelherodev
2c882b2e65
CBE: Make C an ObjectFormat instead of a special bool (#5849) 2020-07-12 22:56:31 -04:00
Vexu
be1507a7af
update compile error tests and some doc comments 2020-07-12 00:54:07 +03:00
Vexu
e85fe13e44
run zig fmt on std lib and self hosted 2020-07-11 20:41:19 +03:00
Andrew Kelley
7bd0500589 Merge remote-tracking branch 'origin/master' into register-allocation 2020-07-08 20:46:06 -07:00
Andrew Kelley
8e425c0c8d stage2: if AST=>ZIR 2020-07-08 20:33:33 -07:00
Noam Preil
6b48634166
CBE: Emit asm decls for now, but rename to make them valid 2020-07-08 14:05:07 -04:00
Andrew Kelley
be0546d877 stage2: implement compare operator AST->ZIR 2020-07-08 07:04:43 +00:00
Andrew Kelley
5e60872060 stage2 misc fixes 2020-07-08 06:56:20 +00:00
Noam Preil
089c056dbe
CBE: Improve resource cleanup 2020-07-07 23:24:30 -04:00
Noam Preil
b91cf15972
CBE: Move standards determination to generated code 2020-07-07 22:57:34 -04:00
Noam Preil
b4c571301b
Stage2: Refactor in preparation for C backend 2020-07-07 14:55:44 -04:00
Andrew Kelley
b55d0193e4 stage2: progress towards Block and CondBr codegen 2020-07-07 08:01:54 +00:00
Andrew Kelley
4d01385e14 fix liveness analysis and not correctly propagating link errors 
We still flush the ELF file even when there are compile errors.
 2020-07-07 03:48:20 +00:00
Andrew Kelley
12737c9a30 stage2: codegen skeleton for cmp and sub 2020-07-06 09:21:57 +00:00
Andrew Kelley
8be8ebd698 stage2: skeleton codegen for x64 ADD 
also rework Module to take advantage of the new hash map implementation.
 2020-07-06 06:10:44 +00:00
Andrew Kelley
8fb392dbb4 stage2: implement liveness analysis 2020-07-05 23:20:08 +00:00
Andrew Kelley
abcd4ea5d8
Merge pull request #5793 from pfgithub/stage-2-testing 
stage2 + operator and @as builtin
 2020-07-05 22:58:05 +00:00
Andrew Kelley
3a89f214aa update more HashMap API usage 2020-07-05 21:11:42 +00:00
pfg
d4456d92f5 stage2: builtin @as 2020-07-04 15:16:46 -07:00
pfg
1d52438bd5 stage2: InfixOp add 2020-07-04 15:16:46 -07:00
Andrew Kelley
ac6bf53069
stage2: clean up test harness, implement symbol collision detection (#5708) 
* Clean up test harness
* Stage2/Testing: Add convenience wrappers
* Add a `compiles` wrapper case
* fix incremental compilation after error
* exported symbol collision detection
* function redefinition detection for Zig code
* handle missing function names
* Stage2/Testing: Simplify incremental compilation tests
* Stage2/Testing: Update documentation
* Stage2/TestHarness: Improve progress reporting
* Disable test
* Improve Tranform failure output
 2020-06-27 21:54:11 -04:00
Noam Preil
80b70470c0
Stage2/Module: Add symbol -> export lookup table 2020-06-27 21:50:59 -04:00
Noam Preil
ffca1569d1
Return instead of branch 2020-06-27 21:39:39 -04:00
Noam Preil
97c41e7152
Disable test 2020-06-27 21:10:44 -04:00
Noam Preil
ab307a22f6
Stage2: remove clearErrors, fix ZIR export collision detection 2020-06-27 07:17:20 -04:00
Noam Preil
c8f60b2e2f
Stage2: handle missing function names 2020-06-26 04:36:17 -04:00
Noam Preil
6510888039
Stage2: function redefinition detection for Zig code 2020-06-26 04:05:41 -04:00
Noam Preil
4a17e008da
Stage2: exported symbol collision detection 2020-06-26 03:17:13 -04:00
Noam Preil
e5a3cb8d71
Stage2: fix incremental compilation after error 2020-06-26 03:16:36 -04:00
Andrew Kelley
130c7fd23b self-hosted: working towards conditional branching test case 
New features:
 * Functions can have parameters in semantic analysis. Codegen
   is not implemented yet.
 * Support for i8, i16, i32, i64, u8, u16, u32, u64 primitive
   identifiers.
 * New ZIR instructions: arg, block, and breakvoid

Implementation details:

 * Move Module.Body to ir.Body
 * Scope.Block gains a parent field and an optional Label field
 * Fix bug in integer type equality comparison.

Here's the test case I'm working towards:

```
@void = primitive(void)
@i32 = primitive(i32)
@fnty = fntype([@i32, @i32], @void)

@0 = str("entry")
@1 = export(@0, "entry")

@entry = fn(@fnty, {
  %0 = arg(0)
  %1 = arg(1)
  %2 = add(%0, %1)
  %3 = int(7)
  %4 = block("if", {
    %neq = cmp(%2, neq, %3)
    %5 = condbr(%neq, {
      %6 = unreachable()
    }, {
      %7 = breakvoid("if")
    })
  })
  %11 = returnvoid()
})
```

$ ./zig-cache/bin/zig build-obj test.zir
test.zir:9:12: error: TODO implement function parameters for Arch.x86_64

That's where I left off.
 2020-06-26 02:30:14 -04:00
Andrew Kelley
5aa3f56773 self-hosted: fix test regressions 
I'm allowing incremental compilation of ZIR modules to be broken. This
is not a real use case of ZIR, and the feature requires a lot of code
duplication with incremental compilation of Zig AST (which works great).
 2020-06-24 20:28:52 -04:00
Andrew Kelley
fd7a97b3b2 fix memory leak of anonymous decl name 2020-06-24 16:20:02 -04:00
Andrew Kelley
14aa08fcd3 self-hosted: restore ZIR functionality 2020-06-24 03:46:32 -04:00