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Author SHA1 Message Date
joachimschmidt557
b2254023e4 stage2: Implement setReg, call, ret, asm for ARM 
These changes enable a Hello World example. However, all implemented
codegen is not yet feature-complete.

- asm only supports 'svc #0' at the moment
- call only supports leaf functions at the moment
- setReg uses a naive method at the moment
 2020-08-23 22:33:47 +02:00
joachimschmidt557
1c53c07053 stage2: Implement genBreakpoint for ARM 2020-08-23 22:29:00 +02:00
joachimschmidt557
f31cee5393 Start working on stage2 ARM backend 
- add codegen/arm.zig with some basic functionality (load/store,
  data processing, branching, software interrupts)
 2020-08-23 22:27:46 +02:00