145 Commits

Author SHA1 Message Date
Alexandros Naskos
e9b137f23a Completed basic PE linker for stage2
Added std.coff.MachineType
Added image characteristic and section flag valued to std.coff
Added std.Target.Cpu.Arch.toCoffMachine
Fixed stage2 --watch flag on windows
2020-09-04 05:15:03 +03:00
Andrew Kelley
f2bbd8a548
Merge pull request #6242 from Vexu/stage2
Stage2: slicing and split container scope from file scope
2020-09-03 17:22:57 -04:00
Jakub Konka
dac1cd7750 Write out simple Mach-O object file
This commit adds enough Mach-O linker implementation to write out simple
Mach-O object file. Be warned however, the object file is largely incomplete:
misses relocation info, debug symbols, etc. However, it seemed like a
good starting to get the basic understanding right.

Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-09-03 16:43:47 -04:00
Vexu
6f0126e957
stage2: split Scope.Container from Scope.File 2020-09-03 15:06:45 +03:00
Vexu
6ab0ac161e
stage2: slice return type analysis 2020-09-03 15:05:47 +03:00
Sahnvour
575fbd5e35 hash_map: rename to ArrayHashMap and add new HashMap implementation 2020-09-02 00:17:50 +02:00
Tadeo Kondrak
d3e5105ecc
std.zig.ast: make getTrailer/setTrailer private and add getters/setters 2020-08-30 17:18:25 -06:00
Vexu
cc26cb9b23 stage2: codegen needed for basic for loop 2020-08-26 19:50:56 -07:00
Andrew Kelley
0c5faa61ae stage2: codegen: fix reuseOperand not doing death bookkeeping 2020-08-26 01:00:04 -07:00
Andrew Kelley
e97157f71c stage2: codegen for conditional branching
* Move branch-local register and stack allocation metadata to the
   function-local struct. Conditional branches clone this data in order
   to restore it after generating machine code for a branch.
   Branch-local data is now only the instruction table mapping *ir.Inst
   to MCValue.
 * Implement conditional branching
   - Process operand deaths
   - Handle register and stack allocation metadata
 * Avoid storing unreferenced or void typed instructions into
   the branch-local instruction table.
 * Fix integer types reporting the wrong value for hasCodeGenBits.
 * Remove the codegen optimization for eliding length-0 jumps. I need to
   reexamine how this works because it was causing invalid jumps to be
   emitted.
2020-08-25 22:44:18 -07:00
Andrew Kelley
b68fa9970b stage2 codegen: Rework genCondBr
so that the arch-independent logic isn't buried and duplicated.
2020-08-25 22:44:18 -07:00
Jakub Konka
9745e7b512 Clean up draft for merging into upstream
Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-08-24 17:59:44 +02:00
Jakub Konka
2516db9645 Specify path to dyld in Mach-O
This is required since an exec on macOS always has to link against
libSystem.dylib.

Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-08-24 17:59:44 +02:00
joachimschmidt557
4f2618e75b stage2: Add Hello World test for ARM backend 2020-08-23 23:13:41 +02:00
joachimschmidt557
b2254023e4 stage2: Implement setReg, call, ret, asm for ARM
These changes enable a Hello World example. However, all implemented
codegen is not yet feature-complete.

- asm only supports 'svc #0' at the moment
- call only supports leaf functions at the moment
- setReg uses a naive method at the moment
2020-08-23 22:33:47 +02:00
joachimschmidt557
1c53c07053 stage2: Implement genBreakpoint for ARM 2020-08-23 22:29:00 +02:00
joachimschmidt557
f31cee5393 Start working on stage2 ARM backend
- add codegen/arm.zig with some basic functionality (load/store,
  data processing, branching, software interrupts)
2020-08-23 22:27:46 +02:00
Noam Preil
24efbf5ddf Codegen: Move REX assert to comptime 2020-08-22 12:45:29 -07:00
Noam Preil
f448b518f8 SPU-II: use undefined1 as breakpoint 2020-08-22 12:45:29 -07:00
Noam Preil
3a9af0c88b SPU-II: Ignore @breakpoint for now 2020-08-22 12:45:29 -07:00
Noam Preil
cdefc6acba SPU-II: Implement function calls 2020-08-22 12:45:29 -07:00
Noam Preil
d005ff16c6 SPU-II: undefined0 inline asm 2020-08-22 12:45:29 -07:00
Andrew Kelley
29051a0674 stage2: codegen: fix crash
I forgot to do -Denable-qemu -Denable-wasmtime when testing yesterday,
sorry about that.

In reuseOperand, the code assumed a re-used register would be tracked in
the register table but that is not always the case.
2020-08-22 12:44:45 -07:00
Andrew Kelley
f18b92ef3a stage2: implement spilling registers to the stack 2020-08-21 23:36:21 -07:00
Andrew Kelley
89b6c47e04 stage2: decouple codegen.zig from ELF
See #6113 for an alternate way of doing this that we didn't end up
following.

Closes #6079.

I also took the opportunity here to extract C.zig and Elf.zig from
link.zig.
2020-08-21 13:25:59 -07:00
Vexu
ebfe723f3c stage2: implement rest of simple pointer types 2020-08-20 16:42:48 -07:00
Vexu
338a495648 stage2: implement global variables 2020-08-19 16:12:29 -07:00
Andrew Kelley
083c0f1ceb stage2 codegen: proper abstraction for re-using dying operands
closes #6064
2020-08-18 23:11:56 -07:00
Andrew Kelley
31b58acdae stage2: minor cleanup 2020-08-18 15:11:24 -07:00
Eleanor Bartle
fa8935426b
Cleaned up RISC-V instruction creation, added 32-bit immediates (#6077)
* Implemented all R-type arithmetic/logical instructions

* Implemented all I-type arithmetic/logical instructions

* Implemented all load and store instructions

* Implemented all of RV64I except FENCE
2020-08-18 00:30:00 -04:00
Vexu
13b2f1e90b
address review feedback 2020-08-17 19:21:03 +03:00
Vexu
ece4a2fc51
stage2: astgen for if and while with error unions 2020-08-17 14:28:04 +03:00
Vexu
012fac255f
stage2: fix optimization causing wrong optional child types 2020-08-17 14:26:32 +03:00
Andrew Kelley
66d76cc4f9 stage2: codegen for labeled blocks 2020-08-15 17:03:05 -07:00
Andrew Kelley
28a9da8bfc stage2: implement while loops (bool condition)
* introduce a dump() function on Module.Fn which helpfully prints to
   stderr the ZIR representation of a function (can be called before
   attempting to codegen it). This is a debugging tool.
 * implement x86 codegen for loops
 * liveness: fix analysis of conditional branches. The logic was buggy
   in a couple ways:
   - it never actually saved the results into the IR instruction (fixed now)
   - it incorrectly labeled operands as dying when their true death was
     after the conditional branch ended (fixed now)
 * zir rendering is enhanced to show liveness analysis results. this
   helps when debugging liveness analysis.
 * fix bug in zir rendering not numbering instructions correctly

closes #6021
2020-08-13 20:32:32 -07:00
Andrew Kelley
ec4953504a stage2: implement safety checks at the zir_sema level 2020-08-13 10:04:46 -07:00
Vexu
6b2ce9d1e9 stage2: split unwrap_optional to safe and unsafe verions 2020-08-13 08:12:17 -07:00
Vexu
4a40282391 stage2: implement unwrap optional 2020-08-13 08:12:17 -07:00
Andrew Kelley
de4f3f11f7 stage2: astgen for while loops
See #6021
2020-08-12 21:13:16 -07:00
Andrew Kelley
8282f4271c stage2: basic support for parameters .debug_info
see #6014
2020-08-11 22:23:32 -07:00
Andrew Kelley
7612931c80 stage2: set up per-Decl .debug_info 2020-08-11 14:07:06 -07:00
Isaac Freund
2fc18b5278 stage2: make link data in Decl into unions
This will allow for implementation of non-Elf backends without wasting
memory.
2020-08-07 19:25:06 -04:00
Noam Preil
a85452b2c2 Codegen: 16-bit pointers 2020-08-05 11:25:43 -07:00
Noam Preil
a5b76d2474 Stage2: minor File.ELF refactor 2020-08-05 11:25:08 -07:00
Andrew Kelley
02d09d1328 codegen: introduce toCanonicalReg to clean up x86-specific logic 2020-08-04 15:31:54 -07:00
pfg
ea3cc777cc stage2: riscv test case 2020-08-04 14:38:33 -07:00
pfg
0b53a2d996 stage2: riscv 0 argument non-nested function calls 2020-08-04 14:38:33 -07:00
pfg
1fd99ed324 stage2: riscv hello world 2020-08-04 14:38:33 -07:00
pfg
52ae2b10aa stage2: starting on a riscv64 backend 2020-08-04 14:38:33 -07:00
Andrew Kelley
331f6a07a9 stage2: fix ZIR support and C back end 2020-08-04 12:15:47 -07:00