40 Commits

Author SHA1 Message Date
Vexu
6ab0ac161e
stage2: slice return type analysis 2020-09-03 15:05:47 +03:00
Sahnvour
575fbd5e35 hash_map: rename to ArrayHashMap and add new HashMap implementation 2020-09-02 00:17:50 +02:00
joachimschmidt557
b2254023e4 stage2: Implement setReg, call, ret, asm for ARM
These changes enable a Hello World example. However, all implemented
codegen is not yet feature-complete.

- asm only supports 'svc #0' at the moment
- call only supports leaf functions at the moment
- setReg uses a naive method at the moment
2020-08-23 22:33:47 +02:00
joachimschmidt557
1c53c07053 stage2: Implement genBreakpoint for ARM 2020-08-23 22:29:00 +02:00
joachimschmidt557
f31cee5393 Start working on stage2 ARM backend
- add codegen/arm.zig with some basic functionality (load/store,
  data processing, branching, software interrupts)
2020-08-23 22:27:46 +02:00
Andrew Kelley
54f3b0a560 stage2: clean up SPU Mk II code
* move SPU code from std to self hosted compiler
 * change std lib comments to be descriptive rather than prescriptive
 * avoid usingnamespace
 * fix case style of error codes
 * remove duplication of producer_string
 * generalize handling of less than 64 bit arch pointers
 * clean up SPU II related test harness code
2020-08-22 13:36:08 -07:00
Noam Preil
f18636fa58 SPU-II: Add common definitions 2020-08-22 12:45:29 -07:00
Noam Preil
cdefc6acba SPU-II: Implement function calls 2020-08-22 12:45:29 -07:00
Isaac Freund
6242ae35f3
stage2/wasm: implement function calls
During codegen we do not yet know the indexes that will be used for
called functions. Therefore, we store the offset into the in-memory
code where the index is needed with a pointer to the Decl and use this
data to insert the proper indexes while writing the binary in the flush
function.
2020-08-19 02:05:13 +02:00
Eleanor Bartle
fa8935426b
Cleaned up RISC-V instruction creation, added 32-bit immediates (#6077)
* Implemented all R-type arithmetic/logical instructions

* Implemented all I-type arithmetic/logical instructions

* Implemented all load and store instructions

* Implemented all of RV64I except FENCE
2020-08-18 00:30:00 -04:00
Isaac Freund
60fb50ee5a
stage2/wasm: write exports on flush, cleanup
Exports now have a dirty flag and are rewritten on flush if this flag
has been set.

A couple other minor changes have been made based on Andrew's review.
2020-08-18 01:01:13 +02:00
Isaac Freund
97300896ed
stage2/wasm: implement trivial codegen
We now generate code for returning constants of any of the basic types.
2020-08-18 01:01:04 +02:00
Isaac Freund
3370b5f109
stage2/wasm: implement basic container generation
Thus far, we only generate the type, function, export, and code
sections. These are sufficient to generate and export simple functions.

Codegen is currently hardcoded to `i32.const 42`, the main goal of this
commit is to create infrastructure for the container format which will
work with incremental compilation.
2020-08-18 00:32:58 +02:00
Noam Preil
34923e071e
CBE: minor doc change 2020-08-16 20:32:50 -04:00
Noam Preil
1eb5aaa4b5 CBE: renderValue pays attention to Type, not Tag 2020-08-12 21:58:21 -07:00
Noam Preil
5a166cead8 CBE: fix handling of IR dependencies 2020-08-12 21:58:21 -07:00
Noam Preil
dbd1e42ef2 CBE: Sorta working intcasts? 2020-08-12 21:58:21 -07:00
Noam Preil
78fe86dcd2 CBE: support unreachable on GCC 2020-08-12 21:58:21 -07:00
Noam Preil
d3eec7d46b CBE: working parameters 2020-08-12 21:58:21 -07:00
Noam Preil
dd1f1487e4 CBE: Use zig_noreturn instead of noreturn to avoid namespace conflict 2020-08-12 21:58:21 -07:00
Andrew Kelley
8282f4271c stage2: basic support for parameters .debug_info
see #6014
2020-08-11 22:23:32 -07:00
Noam Preil
a5b76d2474 Stage2: minor File.ELF refactor 2020-08-05 11:25:08 -07:00
pfg
ea3cc777cc stage2: riscv test case 2020-08-04 14:38:33 -07:00
pfg
0b53a2d996 stage2: riscv 0 argument non-nested function calls 2020-08-04 14:38:33 -07:00
pfg
1fd99ed324 stage2: riscv hello world 2020-08-04 14:38:33 -07:00
pfg
52ae2b10aa stage2: starting on a riscv64 backend 2020-08-04 14:38:33 -07:00
Andrew Kelley
331f6a07a9 stage2: fix ZIR support and C back end 2020-08-04 12:15:47 -07:00
Andrew Kelley
606f157a6b stage2: register-aliasing-aware codegen
* unify duplicated register allocation codepath
 * support the x86_64 concept of register aliasing
 * slightly improved memset codegen, supports sizes 1, 2, 4, 8
2020-07-29 02:29:37 -07:00
Andrew Kelley
b8e22d2002 stage2: implement integer return values 2020-07-27 18:59:13 -07:00
Andrew Kelley
aac6e8c418 self-hosted: AST flattening, astgen improvements, result locations, and more
* AST: flatten ControlFlowExpression into Continue, Break, and Return.
 * AST: unify identifiers and literals into the same AST type: OneToken
 * AST: ControlFlowExpression uses TrailerFlags to optimize storage
   space.
 * astgen: support `var` as well as `const` locals, and support
   explicitly typed locals. Corresponding Module and codegen code is not
   implemented yet.
 * astgen: support result locations.
 * ZIR: add the following instructions (see the corresponding doc
   comments for explanations of semantics):
   - alloc
   - alloc_inferred
   - bitcast_result_ptr
   - coerce_result_block_ptr
   - coerce_result_ptr
   - coerce_to_ptr_elem
   - ensure_result_used
   - ensure_result_non_error
   - ret_ptr
   - ret_type
   - store
   - param_type
 * the skeleton structure for result locations is set up. It's looking
   pretty clean so far.
 * add compile error for unused result and compile error for discarding
   errors.
 * astgen: split builtin calls up to implemented manually, and implement
   `@as`, `@bitCast` (and others) with respect to result locations.
 * add CLI support for hex and raw object formats. They are not
   supported by the self-hosted compiler yet, and emit errors.
 * rename `--c` CLI to `-ofmt=[objectformat]` which can be any of the
   object formats. Only ELF and C are supported so far. Also added missing
   help to the help text.
 * Remove hard tabs from C backend test cases. Shame on you Noam, you
   are grounded, you should know better, etc. Bad boy.
 * Delete C backend code and test case that relied on comptime_int
   incorrectly making it all the way to codegen.
2020-07-23 23:05:26 -07:00
Andrew Kelley
ef91b11295 stage2: register allocator processes operand deaths
also rework the IR data structures
2020-07-20 13:12:20 -07:00
Andrew Kelley
896472c20e stage2: implement register copying 2020-07-20 13:12:20 -07:00
Andrew Kelley
ef9aeb6ac4 stage2: codegen: refactor to always have comptime arch 2020-07-20 13:12:20 -07:00
Andrew Kelley
08154c0deb stage2: add retvoid support to CBE 2020-07-13 00:28:11 -07:00
Andrew Kelley
1eed0cf0f3 zig fmt and delete unused type 2020-06-28 19:45:10 -04:00
Andrew Kelley
aa92446365 stage2: implement function parameters
In codegen.zig, the std.Target.Cpu.Arch is now generally available as a
comptime value where needed. This is a tradeoff that causes the compiler
binary to be more bloated, but gives us higher performance, since the
optimizer can optimize per architecture (which is usually how compilers
are designed anyway, with different code per-architecture), and it also
allows us to use per-architecture types, such as a Register enum that is
specific to the comptime-known architecture.

Adds abiSize method to Type.
2020-06-28 19:45:10 -04:00
Noam Preil
c405844b0a [Stage2/x86] Fix 8-bit register order 2020-06-08 02:28:39 -04:00
Noam Preil
63aa9ffedc [Stage2/Codegen] Typo fix 2020-05-22 15:34:32 -04:00
Noam Preil
a52d1476b7 [Stage2/Codegen] Document x64 register enum layout 2020-05-22 15:32:33 -04:00
Andrew Kelley
88c8ff6e37 move some files around 2020-05-17 12:08:47 -04:00