133 Commits

Author SHA1 Message Date
Jakub Konka
2516db9645 Specify path to dyld in Mach-O
This is required since an exec on macOS always has to link against
libSystem.dylib.

Signed-off-by: Jakub Konka <kubkon@jakubkonka.com>
2020-08-24 17:59:44 +02:00
joachimschmidt557
4f2618e75b stage2: Add Hello World test for ARM backend 2020-08-23 23:13:41 +02:00
joachimschmidt557
b2254023e4 stage2: Implement setReg, call, ret, asm for ARM
These changes enable a Hello World example. However, all implemented
codegen is not yet feature-complete.

- asm only supports 'svc #0' at the moment
- call only supports leaf functions at the moment
- setReg uses a naive method at the moment
2020-08-23 22:33:47 +02:00
joachimschmidt557
1c53c07053 stage2: Implement genBreakpoint for ARM 2020-08-23 22:29:00 +02:00
joachimschmidt557
f31cee5393 Start working on stage2 ARM backend
- add codegen/arm.zig with some basic functionality (load/store,
  data processing, branching, software interrupts)
2020-08-23 22:27:46 +02:00
Noam Preil
24efbf5ddf Codegen: Move REX assert to comptime 2020-08-22 12:45:29 -07:00
Noam Preil
f448b518f8 SPU-II: use undefined1 as breakpoint 2020-08-22 12:45:29 -07:00
Noam Preil
3a9af0c88b SPU-II: Ignore @breakpoint for now 2020-08-22 12:45:29 -07:00
Noam Preil
cdefc6acba SPU-II: Implement function calls 2020-08-22 12:45:29 -07:00
Noam Preil
d005ff16c6 SPU-II: undefined0 inline asm 2020-08-22 12:45:29 -07:00
Andrew Kelley
29051a0674 stage2: codegen: fix crash
I forgot to do -Denable-qemu -Denable-wasmtime when testing yesterday,
sorry about that.

In reuseOperand, the code assumed a re-used register would be tracked in
the register table but that is not always the case.
2020-08-22 12:44:45 -07:00
Andrew Kelley
f18b92ef3a stage2: implement spilling registers to the stack 2020-08-21 23:36:21 -07:00
Andrew Kelley
89b6c47e04 stage2: decouple codegen.zig from ELF
See #6113 for an alternate way of doing this that we didn't end up
following.

Closes #6079.

I also took the opportunity here to extract C.zig and Elf.zig from
link.zig.
2020-08-21 13:25:59 -07:00
Vexu
ebfe723f3c stage2: implement rest of simple pointer types 2020-08-20 16:42:48 -07:00
Vexu
338a495648 stage2: implement global variables 2020-08-19 16:12:29 -07:00
Andrew Kelley
083c0f1ceb stage2 codegen: proper abstraction for re-using dying operands
closes #6064
2020-08-18 23:11:56 -07:00
Andrew Kelley
31b58acdae stage2: minor cleanup 2020-08-18 15:11:24 -07:00
Eleanor Bartle
fa8935426b
Cleaned up RISC-V instruction creation, added 32-bit immediates (#6077)
* Implemented all R-type arithmetic/logical instructions

* Implemented all I-type arithmetic/logical instructions

* Implemented all load and store instructions

* Implemented all of RV64I except FENCE
2020-08-18 00:30:00 -04:00
Vexu
13b2f1e90b
address review feedback 2020-08-17 19:21:03 +03:00
Vexu
ece4a2fc51
stage2: astgen for if and while with error unions 2020-08-17 14:28:04 +03:00
Vexu
012fac255f
stage2: fix optimization causing wrong optional child types 2020-08-17 14:26:32 +03:00
Andrew Kelley
66d76cc4f9 stage2: codegen for labeled blocks 2020-08-15 17:03:05 -07:00
Andrew Kelley
28a9da8bfc stage2: implement while loops (bool condition)
* introduce a dump() function on Module.Fn which helpfully prints to
   stderr the ZIR representation of a function (can be called before
   attempting to codegen it). This is a debugging tool.
 * implement x86 codegen for loops
 * liveness: fix analysis of conditional branches. The logic was buggy
   in a couple ways:
   - it never actually saved the results into the IR instruction (fixed now)
   - it incorrectly labeled operands as dying when their true death was
     after the conditional branch ended (fixed now)
 * zir rendering is enhanced to show liveness analysis results. this
   helps when debugging liveness analysis.
 * fix bug in zir rendering not numbering instructions correctly

closes #6021
2020-08-13 20:32:32 -07:00
Andrew Kelley
ec4953504a stage2: implement safety checks at the zir_sema level 2020-08-13 10:04:46 -07:00
Vexu
6b2ce9d1e9 stage2: split unwrap_optional to safe and unsafe verions 2020-08-13 08:12:17 -07:00
Vexu
4a40282391 stage2: implement unwrap optional 2020-08-13 08:12:17 -07:00
Andrew Kelley
de4f3f11f7 stage2: astgen for while loops
See #6021
2020-08-12 21:13:16 -07:00
Andrew Kelley
8282f4271c stage2: basic support for parameters .debug_info
see #6014
2020-08-11 22:23:32 -07:00
Andrew Kelley
7612931c80 stage2: set up per-Decl .debug_info 2020-08-11 14:07:06 -07:00
Isaac Freund
2fc18b5278 stage2: make link data in Decl into unions
This will allow for implementation of non-Elf backends without wasting
memory.
2020-08-07 19:25:06 -04:00
Noam Preil
a85452b2c2 Codegen: 16-bit pointers 2020-08-05 11:25:43 -07:00
Noam Preil
a5b76d2474 Stage2: minor File.ELF refactor 2020-08-05 11:25:08 -07:00
Andrew Kelley
02d09d1328 codegen: introduce toCanonicalReg to clean up x86-specific logic 2020-08-04 15:31:54 -07:00
pfg
ea3cc777cc stage2: riscv test case 2020-08-04 14:38:33 -07:00
pfg
0b53a2d996 stage2: riscv 0 argument non-nested function calls 2020-08-04 14:38:33 -07:00
pfg
1fd99ed324 stage2: riscv hello world 2020-08-04 14:38:33 -07:00
pfg
52ae2b10aa stage2: starting on a riscv64 backend 2020-08-04 14:38:33 -07:00
Andrew Kelley
331f6a07a9 stage2: fix ZIR support and C back end 2020-08-04 12:15:47 -07:00
Andrew Kelley
a33efc74ed stage2 codegen: revert the unneeded is_stmt stuff 2020-08-03 21:09:58 -07:00
Andrew Kelley
d624bf8059 stage2 .debug_line stepping with gdb is working 2020-08-03 21:01:06 -07:00
Andrew Kelley
ac10841fa9 stage2 .debug_line: simpler strategy for incremental compilation
See #5963
2020-08-03 19:14:09 -07:00
Andrew Kelley
659603c621 codegen: emit .debug_line ops for IR instructions 2020-08-02 21:28:06 -07:00
Andrew Kelley
ba6e5cbfd2 stage2: add the .debug_line header and associated data types
* the .debug_line header is written properly
 * link.File.Elf gains:
   - SrcFn, which is now a field in Module.Fn
   - SrcFile, which is now a field in Module.Scope.File
 * link.File.Elf gets a whole *Package field rather than only
   root_src_dir_path.
 * the fields first_dbg_line_file and last_dbg_line_file tell where the
   Line Number Program begins and ends, which alows moving files when
   the header gets too big, and allows appending files to the end.
 * codegen is passed a buffer for emitting .debug_line
   Line Number Program opcodes for functions.

See #5963

There is some work-in-progress code here, but I need to go make some
experimental changes to changing how to represent source locations and I
want to do that in a separate commit.
2020-08-02 12:02:43 -07:00
Andrew Kelley
8899e6e334 stage2: codegen: fix off-by-one stack variable offsets 2020-07-29 02:29:37 -07:00
Andrew Kelley
606f157a6b stage2: register-aliasing-aware codegen
* unify duplicated register allocation codepath
 * support the x86_64 concept of register aliasing
 * slightly improved memset codegen, supports sizes 1, 2, 4, 8
2020-07-29 02:29:37 -07:00
Andrew Kelley
1bbfa36b76 stage2: improved codegen
* multiple returns jump to one canonical function exitlude. This is in
   preparation for the defer feature.
 * simple elision of trivial jump relocs.
 * omit prelude/exitlude for naked calling convention functions.
 * fix not switching on arch for prelude/exitlude
 * fix swapped registers when setting stack mem from a register
2020-07-29 02:29:37 -07:00
Andrew Kelley
4beff80b2f stage2: codegen handles undefined values
* `optimize_mode` is passed to `link.File` and stored there
 * improve the debugging function `Module.dumpInst`
 * get rid of `Value.the_one_possible_value` in favor of a few more
   specific values for different types. This is less buggy, one less
   footgun.
 * `Type.onePossibleValue` now returns a `?Value` instead of `bool`.
 * codegen handles undefined values. `undef` is a new `MCValue` tag.
   It uses 0xaa values depending on optimization mode. However
   optimization mode does not yet support scope overrides.
 * link.zig: move the `Options` field from `File.Elf` and `File.C` to
   the base struct.
   - fix the Tag enum to adhere to style conventions
 * ZIR now supports emitting undefined values.
 * Fix the logic of comptime math to properly compare against zero using
   the `compareWithZero` function.
2020-07-29 02:29:37 -07:00
Andrew Kelley
cb3e8e323d stage2: x86_64 codegen for movs to/from stack variables 2020-07-29 02:29:37 -07:00
Andrew Kelley
5ccee4c986 stage2: more progress towards mutable local variables
* implement sema for runtime deref, store pointer, coerce_to_ptr_elem,
   and store
 * identifiers support being lvalues, except for decls is still TODO
 * codegen supports load, store, ref, alloc
 * introduce more MCValue union tags to support pointers
 * add load, ref, store typed IR instructions
 * add Type.isVolatilePtr
2020-07-29 02:29:36 -07:00
Andrew Kelley
d726c2a2d3 self-hosted: beginnings of stack allocation
Comment out non-x86_64 architectures for now in codegen.zig, because
they all have compile errors for their codepaths anyway, and it was
bloating the compilation speed and memory usage when stage1 tried to
build self-hosted. Here's the panic message:

"Backend architectures that don't have good support yet are commented
out, to improve compilation performance. If you are interested in one
of these other backends feel free to uncomment them. Eventually these
will be completed, but stage1 is slow and a memory hog."

This is a workaround to lower the time it takes to build self-hosted
with stage1 as well as use less memory. It should fix the CI.

Additionally:
 * Add `single_mut_pointer` support to `Type`
 * Trivial implementation of stack allocation in codegen.zig. It does
   not deal with freeing yet, and it's missing the stack pointer
   adjustment prologue.
 * Add the `alloc` IR instruction and semantic analysis for `alloc` ZIR
   instruction.
2020-07-28 01:43:04 -07:00